Freescale Semiconductor MPC5632M, Руководство пользователя

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MPC563XM Reference Manual, Rev. 1
Freescale Semiconductor 1067
Preliminary—Subject to Change Without Notice
values: 2, 8, 64, or 128 ADC clock cycles. The number of AD conversion cycles is 13 for differential
conversions and 14 for single-ended conversions. The maximum conversion speed is achieved when the
ADC Clock frequency is set to its maximum (15 MHz) and the number of sampling cycles set to its
minimum (2 cycles). The maximum conversion speed for differential and single-ended conversions are
1Msps and 937.5Ksps, respectively.
Table 24-28 shows an example of how the ADC0/1_CLK_PS can be set when using a 120 MHz system
clock and the corresponding conversion speeds for all possible ADC clock frequencies. The table also
shows that according to the system clock frequency, certain clock divide factors are invalid (2, 4, 6, 8 clock
divide factors in the example) since their use would result in a ADC clock frequency higher than the
maximum one supported by the ADC. ADC clock frequency must not exceed 15 MHz.
Table 24-28. ADC Clock Configuration Example (System Clock Frequency=120 MHz)
ADC0/1_CLK_PS[0:4]
System Clock
Divide Factor
ADC Clock
(System Clock =
120 MHz)
Differential
Conversion Speed
with Default Sampling
Time (2 cycles)
Single-Ended
Conversion Speed
with Default Sampling
Time (2 cycles)
0b00000 2 N/A N/A N/A
0b00001 4 N/A N/A N/A
0b00010 6 N/A N/A N/A
0b00011 8 15.0 MHz 1.0 Msps 938 Ksps
0b00100 10 12.0 MHz 800 Ksps 750 Ksps
0b00101 12 10.0 MHz 667 Ksps 625 Ksps
0b00110 14 8.57 MHz 571 Ksps 536 Ksps
0b00111 16 7.5 MHz 500 Ksps 469 Ksps
0b01000 18 6.67 MHz 444 Ksps 417 Ksps
0b01001 20 6.0 MHz 400 Ksps 375 Ksps
0b01010 22 5.45 MHz 364 Ksps 341 Ksps
0b01011 24 5.0 MHz 333 Ksps 313 Ksps
0b01100 26 4.62 MHz 308 Ksps 288 Ksps
0b01101 28 4.29 MHz 286 Ksps 268 Ksps
0b01110 30 4.0 MHz 267 Ksps 250 Ksps
0b01111 32 3.75 MHz 250 Ksps 234 Ksps
0b10000 34 3.53 MHz 235 Ksps 221 Ksps
0b10001 36 3.33 MHz 222 Ksps 208 Ksps
0b10010 38 3.16 MHz 211 Ksps 198 Ksps
0b10011 40 3.0 MHz 200 Ksps 188 Ksps
0b10100 42 2.86 MHz 190 Ksps 179 Ksps
0b10101 44 2.73 MHz 182 Ksps 170 Ksps
0b10110 46 2.61 MHz 174 Ksps 163 Ksps
0b10111 48 2.5 MHz 167 Ksps 156 Ksps
0b11000 50 2.4 MHz 160 Ksps 150 Ksps
ADCConversionSpeed
ADCClockFrequency MHz
( )
NumberOfSamplingCycles NumberOfADConversionCycles +
( )
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