M
ODEL
SDP100 V
ERSION
V_1.00
P
REPARED BY
H/W
D
ATE
25/05/2007
S
UBJECT
T
ECHNICAL
M
ANUAL
P
AGE
2/70
z
General
-. Integrated voice-band, audio-band and base-band analog front ends.
-. TFBGA 13mm x 13mm, 314balls, 0.65mm pitch package.
z
MCU Subsystem
-. ARM7EJ-S 32bit RISC processor
-. High Performance Multi-layer AMBA bus
-. Java hardware acceleration for fast Java-based games and applets.
-.Operating frequency : 25/52/104Mhz
-. Dedicated DMA Bus
-. 14 DMA channels
-. 1M bits on-chip SRAM
-. 1M bits MCU dedicated Tightly Coupled memory
-. 256K bits CODE cache
-. 64K bits DATA cache
-. On-chip boot ROM for factory flash programming
-. Watchdog timer for system crash recovery
-. 3sets of General purpose timer
-. Circuit Switch Data coprocessor
-. Division coprocessor
-. PPP Framer coprocessor
z
External Memory Interface
-. Supports up to 4 external devices
-. Supports 8-bit or 16-bit memory components with maximum size of up to 64M bytes each.
-. Supports Mobile RAM and Cellular RAM
-. Supports Flash and SRAM/PSRAM with page mode or burst mode
-. Industry standard Parallel LCD interface
-. Supports Multi-media companion chips with 8/16bits data width.
-. Flexible I/O voltage of 1.8V ~ 2.8V for memory interface.
z
User Interface
-. 6-row x 7-column keypad controller with hardware scanner.
-. Supports multiple key presses for gaming.
-. SIM/USIM controller with hardware T=0/T=1 protocol control.
-. Real Time Clock(RTC) operating with a separate power supply.
-. General Purpose I/Os (GPIOs)
-. 2sets of Pulse Width Modulation(PWM) output.
-. Alerter Output with enhanced PWM or PDM.
-. 8 external interrupt lines.
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Security
-. Cipher : supports AES, DES/3DES
SDP100
T
ECHNICAL
M
ANUAL
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