Theory of Operation
Inguard Software Description
2
2-53
After the input channel has been selected and the Stallion chip programmed
appropriately, there is a minimum time required for the signal conditioning circuitry to
settle. This settling time varies depending on the function and range being measured, and
is given in Table 2-18: Signal Conditioning Settling Time.
Table 2-18. Signal Conditioning Settling Time
Function
Time
VDC
30
µ
s
VAC, fast
100 ms
VAC, medium
150 ms
VAC, slow
200 ms
300
Ω
20
µ
s
3 k
Ω
100
µ
s
30 k
Ω
400
µ
s
300 k
Ω
2 ms
3 M
Ω
10 ms
Frequency, fast
100 ms
Frequency, medium
150 ms
Frequency, slow
200
µ
s
Zero, BR1
30
µ
s
Zero, BR2
30
µ
s
Zero, BR3
30
µ
s
Zero, BR4
30
µ
s
Reference Balance, both references on
30
µ
s
Reference Balance, both references off
30
µ
s
Reference Junction
30
µ
s
A/D
2-96.
The multi-slope A/D converter in the instrument uses a hardware state machine (A3U18)
to control the switching of the voltage references during the A/D conversion. This state
machine also contains the counters that measure how long each reference is switched in,
and provides the A3U5 A/D microprocessor with its interface to the A/D. A synchronous
serial port is used to transfer the counter contents from the state machine to the A3U5
A/D microprocessor. These counter values can then be manipulated to form an A/D
reading. There are two counters, NCOUNT and PCOUNT, which measure how long the
negative and positive references, respectively, are switched in.
Содержание NetDAQ 2640A
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