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Theory of Operation
Detailed Circuit Description
2
2-29
Watchdog Timer and Reset Circuit
2-53.
The Watchdog Timer and Reset circuit has been defeated by the insertion of the jumper
between TP1 and TP3 on the Display Assembly. In this instrument, the reset circuitry is
on the Main Assembly and the Watchdog Timer is part of the Microprocessor (A1U1).
The Display Reset signal (DRST*) drives the RESET2* signal on the Display Assembly
low when the instrument is being reset. This discharges capacitor A2C3, and NAND gate
output A2U6-11 provides an active high reset signal to the Display Processor. The
Watchdog Timer on the Display Assembly (A2U5, A2U6 and various resistive and
capacitive timing components) is held "cleared" by TP1 being held at 0V dc by a jumper,
and output A2U5-12 is high.
Display Controller
2-54.
The Display Controller is a four-bit, single-chip microcomputer with high-voltage
outputs that are capable of driving a vacuum-fluorescent display directly. The controller
receives commands over a three-wire communication channel from the Microprocessor
on the Main Assembly. Each command is transferred serially to the Display Controller
on the display transmit (DISTX) signal, with bits being clocked into the Display
Controller on the rising edges of the display clock signal (DSCLK). Responses from the
Display Controller are sent to the Microprocessor on the display receive signal (DISRX)
and are clocked out of the Display Controller on the falling edge of DSCLK.
Series resistor A2R11 isolates DSCLK from A2U1-40, preventing this output from
trying to drive A1U4-16 directly. Figure 2-4 shows the waveforms during a single
command byte transfer. Note that a high DISRX signal is used to hold off further
transfers until the Display Controller has processed the previously received byte of the
command.
BIT 7
BIT 7
HOLD OFF
CLEAR TO
RECEIVE
31.5 µs
DISTX
DSCLK
DISRX
CLEAR TO
RECEIVE
31.5 µs
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Figure 2-4. Command Byte Transfer Waveforms
Once reset, the Display Controller performs a series of self-tests, initializing display
memory and holding the DISRX signal high. After DISRX goes low, the Display
Controller is ready for communication; on the first command byte from the
Microprocessor, the Display Controller responds with a self-test results response. If all
self-tests pass, a response of 00000001 (binary) is returned. If any self-test fails, a
response of 01010101 (binary) is returned. The Display Controller initializes its display
memory to one of four display patterns depending on the states of the DTEST*
(A2U1-41) and LTE* (A2U1-13) inputs. The DTEST* input is pulled up by A2Z1, but
may be pulled down by jumpering A2TP4 to A2TP3 (GND). The LTE* input is pulled
down by A2R12, but may be pulled up by jumpering A2TP5 to A2TP6 (Vcc). The
default conditions of DTEST* and LTE* cause the Display Controller to turn all
segments on bright at power-up.
Содержание NetDAQ 2640A
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Страница 225: ...List of Replaceable Parts Parts Lists 6 6 21 2640A 1603 Figure 6 4 2640A A3 A D Converter PCA Assembly...
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Страница 242: ...2640A 2645A Service Manual 7 10 Figure 7 2 A2 Display PCA Assembly 2620A 1602...
Страница 243: ...Schematic Diagrams 7 7 11 Figure 7 2 A2 Display PCA Assembly cont 2620A 1002...
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Страница 251: ...Schematic Diagrams 7 7 19 2645A 1603 Figure 7 4 2645A A3 A D Converter PCA Assembly 2645A 1603...
Страница 258: ...2640A 2645A Service Manual 7 26 Figure 7 5 A4 Analog Input PCA Assembly 2620A 1604...
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