Fluke NetDAQ 2640A, Руководство по обслуживанию

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Theory of Operation
Detailed Circuit Description
2
2-19
Real-Time Clock 2-37.
The Real-Time Clock maintains time and calendar date information for use by the
instrument.
A nonvolatile power supply (Vbb) biases A1U11. The Microprocessor Supervisor
(A1U10) monitors the voltage on Vcc (A1U10-2). If Vcc is greater than the voltage of
the lithium battery (A1U10-8), A1U10 switches Vcc from A1U10-2 to A1U10-1 (Vbb).
If Vcc drops below the voltage of the lithium battery (A1U10-8), A1U10 switches
voltage from lithium battery A1BT1 through current-limiting resistor A1R84 to
A1U10-1 (Vbb). The nominal current required from the lithium battery (A1BT1) at room
temperature with the instrument powered down is approximately 2 microamperes. This
can be easily measured by checking the voltage across A1R98.
Memory accesses to the Real-Time Clock (A1U11) are enabled by the RTC address
decode output (A1U29-16). This signal must go through a NAND gate in A1U36 to the
Real-Time Clock chip select input (A1U11-18). This ensures that when the instrument is
powered down and A1U10-7 is driven low, A1U11-18 is driven high so that the contents
of the Real-Time Clock cannot be changed, and the power dissipated by the Real-Time
Clock is minimized. A1U11 is connected to the high 8 bits of the data bus, so read
accesses are enabled by the Read Lower (RD1*;A1U11-19) signal going low, and write
accesses are enabled by the Write Upper (WRU*;A1U11-20) signal going low. When
the instrument is powered up, the accuracy of the timebase generated by the internal
crystal may be tested by measuring the frequency of the 1-Hz square wave output
(A1U11-4). The Real-Time Clock also has an interrupt output (A1U11-3) that is used by
the Microprocessor to synchronize its internal millisecond timer to the real-time clock.
There should be 64 interrupts per second from the real-time clock.
FPGA (Field Programmable Gate Array) 2-38.
When the instrument is powered up, the FPGA, a complex programmable logic device,
clears its configuration memory and waits until RESET* (A1U31-78) goes high. The
FPGA then tests its mode pins and should determine that it is in "peripheral"
configuration mode (A1U31-54 high; A1U31-52 low; A1U31-56 high). In this mode the
Microprocessor must load the configuration information into the FPGA before the FPGA
logic can begin operation.
The Microprocessor first makes sure that the FPGA is ready to be configured by driving
XD/P* (A1U31-80) low and then pulsing the RESET* (A1U31-78) input low for about
10 microseconds. The Microprocessor then waits until the XINIT* (A1U31-65) output
goes high, indicating that the FPGA has been initialized and is ready for configuration.
The Microprocessor then writes a byte of configuration data to the FPGA by driving
PGA* (A1U31-88) low and latching the data on the data inputs (D<0> through D<7>) by
pulsing WRL* (A1U31-5) low and then back high. The XRDY (A1U31-99) output then
goes low to indicate that the FPGA is busy loading that configuration byte. The
Microprocessor then waits until XRDY goes high again before loading the next
configuration byte, and the sequence is repeated until the last byte is loaded. While the
configuration data is being loaded, the FPGA drives the XD/P* signal (A1U31-80) low.
When the FPGA has been completely configured, the XD/P* signal is released and
pulled high by resistor A1R64. The Microprocessor repeats the configuration sequence if
XD/P* (A1U31-80) does not go high when it is expected to.