Fluke NetDAQ 2640A, Руководство по обслуживанию

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NetDAQ
Service Manual
2-14
Reset Circuits 2-32.
The Power-On Reset signal (POR*, A1U10-7) is generated by the Microprocessor
Supervisor, which monitors the voltage of Vcc at A1U10-2. If Vcc is less than +4.65
volts, then A1U10-7 is driven low. POR* drives the enable inputs of the four tri-state
buffers in A1U2, causing the HALT*, RESET*, and DRST* signals to be driven low
when POR* is low. When POR* goes high, the tri-state buffer outputs (A1U2) go to
their high-impedance state and the pull-up resistors pull the outputs to a high level.
When HALT* and RESET* are both driven low, the Microprocessor (A1U1) is reset and
is in execution when they both go high. The Microprocessor may execute a "reset"
instruction during normal operation to drive A1U1-92 low for approximately 10
microseconds to reset all system hardware connected to the RESET* signal.
The Display Reset signal (DRST*) is driven low by A1U2-6 when POR* is low, or it
may be driven low by the Microprocessor (A1U1-56) if the instrument firmware needs to
reset only the display hardware. For example, the firmware resets the display hardware
after the FPGA is loaded at power-up and the Display Clock (DCLK) signal from the
FPGA begins normal operation. This ensures that the Display Processor is properly reset
while DCLK is active.
Microprocessor 2-33.
The Microprocessor uses a 16-bit data bus and a 20-bit address bus to access locations in
the Flash Memory (A1U21), the Static RAM (A1U20, A1U30, A1U34 and A1U35), the
Real-Time Clock (A1U11), the FPGA (A1U31), and the Ethernet Interface (A1U32). All
of the data bus lines and the lowest 12 address lines have series termination resistors
located near the Microprocessor (A1U1) to ensure that the instrument meets EMI/EMC
performance requirements. When a memory access is done to the upper half of the data
bus (D15 through D8), the upper data strobe (UDS*) goes low. When a memory access
is done to the lower half of the data bus (D7 through D0), the lower data strobe (LDS*)
goes low. When a memory access is a read cycle, R/W* must be high. Conversely for
any write cycle, R/W* must be low.
The Microprocessor is a variant of the popular Motorola 68000 processor and is
enhanced by including hardware support for clock generation, address decoding, timers,
parallel ports, synchronous and asynchronous serial communications, interrupt
controller, DMA (Direct Memory Access) controllers, and a watchdog timer.
The 15.36-MHz system clock signal (A1TP11) is generated by the oscillator circuit
composed of A1U1, A1Y1, A1R2, A1C3, and A1C8. This clock goes through a series
termination resistor (A1R17) to the FPGA (A1U31). This resistor is necessary to ensure
that the instrument meets EMI/EMC performance requirements.
The Microprocessor has four software programmed address decoders that include wait
state control logic. These four outputs are used to enable external memory and I/O
components during read and write bus cycles. See "Address Decoding" for a complete
description.