Fluke NetDAQ 2640A, Руководство по обслуживанию

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NetDAQ
Service Manual
2-20
The FPGA contains the following eight functional elements after the Microprocessor has
loaded the configuration into the FPGA:
•
Clock Dividers
•
Internal Register Address Decoding
•
Keyboard Scanner
•
Digital I/O Buffers
•
Latches
•
Totalizer Debouncing and Mode Selection
•
Totalizer Counter
•
External Trigger Logic
Clock Dividers The 15.36-MHz system clock (A1U31-30) is divided down by the
Clock Dividers to create the 1.024-MHz Display Clock (DCLK; A1U31-19). The
Display Clock is not a square wave; it is low for 2/3 of a cycle and high for the other 1/3.
The Display Clock is also used internal to the FPGA to create the 128-kHz Totalizer
Debouncer Clock and the 4-kHz Keyboard Scanner Clock.
Internal Register Address Decoding The FPGA logic decodes four bits of the address
bus (A<3> through A<6>), the PGA* chip select signal (A1U31-88), RD2* (A1U31-95),
and WRL* (A1U31-5) to allow the Microprocessor to read five registers and write to
three registers implemented in the FPGA logic. The absolute addresses are listed in
Table 2-3.
Keyboard Scanner The Keyboard Scanner sequences through the array of switches on
the Display Assembly to detect and debounce switch closures. After a switch closure is
detected, it must remain closed for at least 16 milliseconds before the Microprocessor is
interrupted and the Keyboard Input register is read from the FPGA. When the keyboard
interrupt (KINT*, A1U31-62) goes low, the Keyboard Scanner stops scanning until the
Microprocessor reads the Keyboard Input register, which automatically clears the
interrupt by driving KINT* high again. The FPGA interrupts the Microprocessor again
when the switch on the Display Assembly is detected as open again. Actually the
Microprocessor is interrupted once for each debounced change in the contents of the
Keyboard Input register. See also the information on "Front Panel Switches" in the
"Display PCA" section for this instrument.
The Microprocessor can enable or disable the Keyboard Scanner by changing the state of
a bit in the Control/Status register that is in the FPGA. The Keyboard Scanner is disabled
if the instrument is in either the RWLS or LWLS state (see Users Manual; RWLS, and
LWLS Computer Interface Commands).
Digital I/O Buffers and Latches The FPGA logic implements internal registers for the
eight Digital Outputs (DO<0> through DO<7>), Master Alarm Output (AO<2>), and
Trigger Output (AO<3>). The two Alarm Outputs (AO<0> and ADO<1>) are not
supported. These registers are both written and read by the Microprocessor. The FPGA
logic also implements an eight-bit input buffer so that the Microprocessor can read the
eight Digital Input lines (DI<0> through DI<7>). See also "Digital Input Buffers" and
"Digital and Alarm Output Drivers."