TAN-042
Designing the XRT71D00 and the XRT73L00 Devices to
operate in the Host Mode, and to be accessed via a single Chip
Select pin.
Preliminary
July 19, 2001
Revision 1.03
48
Bits 6 and 7:
The next two bits, A4 and A5 must be set to “0”, as shown in Figure 23.
Bit 8 - A6
The value of “A6” is a “don’t care”.
Once these first 8 bits have been written into the Microprocessor Serial Interface, the
subsequent action depends upon whether the current operation is a “Read” or “Write”
operation.
Read Operation
Once the last address bit (A3) has been clocked into the SDI input, the “Read” operation
will proceed through an idle period, lasting three SCLK periods. On the falling edge of
SCLK Cycle #8 (see Figure 28) the serial data output signal (SDO) becomes active. At
this point the user can begin reading the data contents of the addressed Command
Register (at Address [A3, A2, A1, A0]) via the SDO output pin. The Microprocessor
Serial Interface will output this five-bit data word (D0 through D4) in ascending order
(with the LSB first), on the falling edges of the SCLK pin. As a consequence, the data
(on the SDO output pin) will be sufficiently stable for reading (by the Microprocessor),
on the very next rising edge of the SCLK pin.
Write Operation
Once the last address bit (A3) has been clocked into the SDI input, the “Write” operation
will proceed through an idle period, lasting three SCLK periods. Prior to the rising edge
of SCLK Cycle # 9 (see Figure 28) the user must begin to apply the eight-bit data word,
that he/she wishes to write to the Microprocessor Serial Interface, onto the SDI input pin.
The Microprocessor Serial Interface will latch the value on the SDI input pin, on the
rising edge of SCLK. The user must apply this word (D0 through D7) serially, in
ascending order with the LSB first.
