TAN-042
Designing the XRT71D00 and the XRT73L00 Devices to
operate in the Host Mode, and to be accessed via a single Chip
Select pin.
Preliminary
July 19, 2001
Revision 1.03
14
2. The XRT71D00 device has been designed to operate in the Receive Path (Figure
4)
Figure 4 presents a schematic design in which the Jitter Attenuator is placed in the
“Receive Path” such that the “RPOS”, “RNEG” and “RCLK” output signals (from the
XRT73L00 LIU IC) are being routed to the “RPOS”, “RNEG” and “RCLK” input signals
of the XRT71D00 Jitter Attenuator IC.
3. The XRT71D00 device has been designed to operate in the Transmit Path (Figure
6).
It should be noted that it is entirely acceptable to design a board such that the Jitter
Attenuator is placed in the “Transmit Path”; as is shown in Figure 6. Please note that in
this case, the “RRPOS”, “RRNEG” and “RRCLK” outputs (from the XRT71D00 Jitter
Attenuator IC) are being routed to the “TPDATA”, “TNDATA” and “TCLK” input
signals of the LIU IC.
