TAN-042
Designing the XRT71D00 and the XRT73L00 Devices to
operate in the Host Mode, and to be accessed via a single Chip
Select pin.
Preliminary
July 19, 2001
Revision 1.03
18
4.2 DESIGN CONSIDERATIONS WHEN THE JITTER
ATTENUATOR IS DESIGNED IN THE TRANSMIT PATH
If the user has designed his/her board such that the XRT71D00 device is operating in the
“Transmit Path” (as illustrated in Figure 6), then it is imperative that the two devices be
configured such that the “set-up” and “hold” time requirements (of the
TPDATA/TNDATA inputs of the XRT73L00 device) are met.
By default, the XRT73L00 device will sample the data, input at the
“TPDATA/TNDATA” pins, upon the falling edge of “TCLK”. According to the
XRT73L00 Data Sheet, the “TPDATA/TNDATA to TCLK” set-up time requirements are
3ns (minimum). Additionally, the “TCLK to TPDATA/TNDATA” hold time
requirements are also 3ns (minimum). According to the XT71D00 Data Sheet, the
“RRPOS/RRNEG to RRCLK” output delay is 5ns (maximum). Therefore, the user is
advised to configure the XRT71D00 device to output the “RRPOS/RRNEG” data upon
the rising edge of “RRCLK”.
In order to achieve this configuration, the user must insure that the “TXCLK INV” bit-
field (within the XRT73L00 device) is set to “0”, and that the “CLKES” bit-field (within
the XRT71D00 device) is set to “1”; as illustrated below.
