TAN-042
Designing the XRT71D00 and the XRT73L00 Devices to
operate in the Host Mode, and to be accessed via a single Chip
Select pin.
Preliminary
July 19, 2001
Revision 1.03
43
Setting this bit-field to “0” configures the XRT71D00 device to operate in either the
“DS3” or “E3” Modes. In this setting the state of the “D4” (E3/DS3*) bit-field will
dictate whether the chip is operating in the DS3 or E3 Mode.
Command Register CR7 (CR15 or CR23)
Bit D0 – FL
This “Read-Only” bit-field permits the user to determine if the XRT71D00 device is
currently declaring a “FIFO Alarm” event. If the FIFO READ and WRITE pointers
come within two bit-positions or each other, then the XRT71D00 device will declare a
“FIFO Alarm” event. The purpose of this “FIFO Alarm” event is to alert the system that
the FIFO (within the XRT71D00 device) is about to “Under-flow” or “Over-flow”.
NOTES:
1. This bit-field (and the corresponding output pins) will only be set to “high”
whenever the “FIFO READ” and “FIFO WRITE” pointers are CURRENTLY
within two bit-positions of each other. This bit-field will be reset to “0” whenever
the “FIFO READ” and “FIFO WRITE” pointers move to beyond two bit-
positions of each other.
2. This bit-field can be used as an indication that the “Jitter Attenuator” PLL has lost
“lock” with the “RCLK” input signal.
