TAN-042
Designing the XRT71D00 and the XRT73L00 Devices to
operate in the Host Mode, and to be accessed via a single Chip
Select pin.
Preliminary
July 19, 2001
Revision 1.03
9
3.0 THE CHANNEL ASSIGNMENT FEATURE OF THE
XRT71D00 DEVICE
The “Channel Assignment” feature, within the XRT71D00 device, permits the user to
perform “READ/WRITE” access to the following sets of devices, with only one Chip
Select pin.
•
1- XRT73L00 1-Channel DS3/E3/STS-1 LIU IC and 1-XRT71D00 DS3/E3/STS-1
Jitter Attenuator IC.
•
1-XRT7300 1-Channel DS3/E3/STS-1 LIU IC and 1-XRT71D00 DS3/E3/STS-1 Jitter
Attenuator IC.
•
1- XRT73L02 2-Channel DS3/E3/STS-1 LIU IC and 2-XRT71D00 DS3/E3/STS-1
Jitter Attenuator Devices.
•
1-XRT7302 2-Channel DS3/E3/STS-1 LIU IC and 2-XRT71D00 DS3/E3/STS-1 Jitter
Attenuator Devices.
•
1-XRT73L03 3-Channel DS3/E3/STS-1 LIU IC and 3-XRT71D00 DS3/E3/STS-1
Jitter Attenuator Devices.
Figure 2 presents the bit format of the Command Registers, within the XRT71D00
device. In this figure, the Command Register set is sub-divided into “Channels”.
Command Registers CR6 and CR7 are allocated to “Channel 0”; Command Registers
CR14 and CR15 are allocated to “Channel 1”; and finally, Command Registers CR22 and
CR23 have been allocated to “Channel 2”. The XRT71D00 device contains two external
input pins, which are relevant to this discussion.
•
Ch_Addr_0 (Pin 28)
•
Ch_Addr_1 (Pin 15)
A XRT71D00 device (within a given system) can be assigned a “Channel Number” by
setting the “Ch_Addr_0” and “Ch_Addr_1” input pins either high or low. The
relationship between the states of the “Ch_Addr_0” and the “Ch_Addr_1” input pins, and
the “Assigned Channel” is presented below in Table 1.
