TAN-042
Designing the XRT71D00 and the XRT73L00 Devices to
operate in the Host Mode, and to be accessed via a single Chip
Select pin.
Preliminary
July 19, 2001
Revision 1.03
15
4.1 DESIGN CONSIDERATIONS WHEN THE JITTER
ATTENUATOR IS DESIGNED IN THE RECEIVE PATH
If the user has designed his/her board such that the XRT71D00 device is operating in the
“Receive Path” (as illustrated in Figure 4), then it is imperative that the two devices be
configured such that the “set-up” and “hold” time requirements (of the RPOS/RNEG
inputs of the XRT71D00 device) are met.
By default, the XRT73L00 device will update its “recovered” data, via the “RPOS” and
“RNEG” output pins, upon the rising edge of “RCLK1” and “RCLK2”. According to the
XRT73L00 Data Sheet, the “RCLK to RPOS/RNEG” output delay is about 4ns
(maximum). Therefore, the user is advised to configure the XRT71D00 device to sample
the data, via its “RPOS” and “RNEG” input pins, upon the falling edge of the “RCLK”
input signal. According to the XRT71D00 Data Sheet, the “RPOS/RNEG” to “RCLK”
set-up and hold time requirements are each 3ns (maximum).
In order to achieve this configuration, the user must insure that the “RCLK1” or
“RCLK2” bit-fields (within the XRT73L00 device) are set to “0”, and that the “CLKES”
bit-field (within the XRT71D00 device) is set to “1”; as illustrated below.
