TAN-042
Designing the XRT71D00 and the XRT73L00 Devices to
operate in the Host Mode, and to be accessed via a single Chip
Select pin.
Preliminary
July 19, 2001
Revision 1.03
7
2.2 BACKGROUND INFORMATION – THE XRT71D00 1-
CHANNEL DS3/E3/STS-1 JITTER ATTENUATOR IC
The XRT71D00 device is a single-channel DS3/E3/STS-1 Jitter Attenuator IC that was
designed to operate at either 3.3V or 5V. Further, this device can be configured via two
possible approaches.
a. The Hardware Mode
b. The Host Mode
If the XRT71D00 device has been configured to operate in the “Hardware” Mode, then
all Mode/Configuration selection is achieved by setting certain input pins either “HIGH”
or “LOW”. If the user configures the XRT71D00 device to operate in the “Hardware”
Mode, the user can configure the XRT71D00 device into a wide variety of modes, via the
following external input pins.
•
FSS – FIFO Size Select
•
DJA – Disable (Jitter Attenuator PLL) Select
•
CLKES – Clock Edge Select
•
BWS – (Jitter Attenuator PLL) Bandwidth Select
•
DS3*/E3 – Data Rate Select Input pin
•
STS-1 – Data Rate Select Input pin.
Therefore, for Hardware Mode operation, the XRT71D00 device provides the user with 6
input pins that can be used to control various operational aspects of the XRT71D00
device.
If the XRT71D00 device has been configured to operate in the “Host” Mode, then all
Mode/Configuration is achieved by writing data into the on-chip Command Registers
(via the Microprocessor Serial Interface block). The Microprocessor Serial Interface
block consists of the following pins.
•
SDI – Serial Data In
•
SDO – Serial Data Out
•
SCLK – Serial Clock Input
•
CS* - Chip Select Input
•
RST* - Reset Input
A more detailed description of each of these pins is presented in Appendix C.
