Distributor of Equinox Technologies: Excellent Integrated System Limited
Datasheet of ISPNANO S3 KIT - ISP PORTABLE PROGRAMMER
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ISPnano Series Programmer - User Manual – V1.11 – 12
th
May 2011
110
3.5 ATE Port
Target ISP Port – Pin routing (RELAYs OFF)
By default the RELAYs are
OFF
and the
‘ATE Port’
signals are routed to the
‘Target ISP Port’
pins
as detailed in the table below.
Target ISP
Port
Pin Number
ATE Port
Pin
Number
Programmer
Pin name
Notes
1 + 2
13 + 14
TARGET_VCC
Target VCC
This pin should be connected to the Target
System Vcc.
3 + 4
No
connection
EXT_VCC
Target External VCC
No connection required as EXT-VCC is
being used to control the RELAY coils.
5 + 6
11 + 12
PROG_GND
Signal Ground Connection (1)
0V to which the programmer JTAG, SPI,
I2C, PDI, TPI signal lines are referenced
to.
7a
7b
7c
8a
8b
8c
•
I2C SCL
•
PDI_CLK
•
TPI_CLK
•
I2C SCL clock signal
•
XMEGA PDI CLOCK Signal
•
ATtiny TPI CLOCK Signal
8a
8b
8c
7a
7b
7c
•
I2C_SDA
•
XMEGA_PDI_DATA
•
ATTINY_TPI_DATA
•
I2C SDA data signal
•
XMEGA PDI DATA Signal
•
ATtiny TPI DATA Signal
9
6
OP6
Spare Output (used for PDI / TPI)
10
5
Programmer I/O5
Spare I/O pin
11
4
Programmer I/O4
This pin is used for JTAG Target Systems
only.
12
3
Programmer I/O3
This pin can be used for JTAG or SPI
Target Systems.
13
2
Programmer I/O2
This pin can be used for JTAG, SPI,
UART, XMEGA PDI and ATtiny TPI Target
Systems.
14
1
Programmer I/O1
This pin can be used for JTAG, SPI or
UART Target Systems.
15
10
PROG_VPP
Vpp Voltage
16
9
PROG_RESET
Target RESET control pin
127 / 135
127 / 135
