Elan eSL Series, Руководство пользователя

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Chapter 3
eSL/eSLS Series (+ eSLZ000) User’s Manual Peripheral Control
••••
81
Timer 2 Control ( TCON2) Registers Attributes and Definitions:
TCON2 Bit DIR. Description
Reset
Value
TEN2 [15] R/W
Timer Enable (this bit enables or disables Timer
functions)
:
0: Disable (Stop)
1: Enable (Start)
0
TC2 [6] R/W
Timer counter clear (TCNT) :
0: No effect
1: Clear TCNT
0
TIOM2 [5:4] R/W
When TM2 = 0 (Compare) :
00: No output at compare match (TIF2)
01: Output toggles to the TCCP pin and reset
TCNT at TCCR compare match (TIF2)
10:
Output toggles to the TCCP pin at TCCR
compare match (TIF2, TVIF2)
11: Output simple PWM to the TCCP pin at
TCCR compare match (TIF2, TVIF2)
When TM2 = 1 (Capture) :
00: Input capture at rising edge of the TCCP pin
01: Input capture at falling edge of the TCCP pin
1X: Input capture at rising and falling edges of
the TCCP pin
00
TM2 [3] R/W
Selects TCCR function :
0: TCCR functions as an output compare register
1: TCCR functions as an input capture register
0
TCS2 [2:0] R/W
000: F
PLL
/256
001: F
PLL
/512
010: F
PLL
/1024
011: F
PLL
/2048
100: F
PLL
/4096
101: TEXI2 rising edge
110: TEXI2 falling edge
111: F
32k
OSC
000
NOTE
In order to latch the external clock, TEXI2 clock speed must be under 16kHz when in
SLOW mode and under 1/2 system clock when in NORMAL mode.
SLOW mode does NOT support TCS2=111 32K OSC input.
In order to latch the external input, TCCP2_input speed must be under 16kHz when
in SLOW mode and under 1/2 system clock when in NORMAL mode.