Elan eSL Series, Руководство пользователя

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Chapter 3
eSL/eSLS Series (+ eSLZ000) User’s Manual Peripheral Control
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3.8.4 SPI Register
SPI Register Attributes and Definitions :
Name Function DIR. Default
RDBR 16-bit Receive Data Buffer Register R 0x0
TDBR 16-bit Transmit Data Buffer Register R/W 0x0
SFDR 16-bit Data Shift Register -- --
SPICON Serial Peripheral Control Register R/W 0x0
SPISR Serial Peripheral Status Register R 0x0
3.8.4.1 Receive Data Buffer Register (RDBR)
The Receive Data Buffer Register (RDBR) is a 16-bit read-only (RO) register.
At the end of a data transfer, the data in the shift register is loaded into RDBR.
3.8.4.2 Transmit Data Buffer Register (TDBR)
The Transmit Data Buffer Register (TDBR) is a readable and writeable register.
Data is loaded into this register before being transmitted. Just prior to the
beginning of a data transfer, the data in TDBR is loaded into the Shift Data
(SFDR) register.
NOTE
When SPI module is enabled, transmission does not start immediately. Only when data
is written into TDBR that transmission is initiated.
If multiple write to TDBR occurs while a data transfer is in progress, only the
last written data will be transmitted. None of the intermediate values written to
TDBR will be transmitted. Multiple write to TDBR are possible but not
recommended.
3.8.4.3 Shift Data Register (SFDR)
The Data Shift Register (SFDR) is the 16-bit data shift register ( it is not
accessible by software ). The SFDR is buffered to prevent a write to TDBR
from overwriting the shift register during an active transfer.
The data in SFDR is shifted out (MSB) on subsequent SCK cycles. For every
bit (MSB) shifted out of the SPI, a bit is shifted into the LSB end of the shift
register.