Chapter 3
132
••••
Peripheral Control
eSL/eSLS Series (+ eSLZ000) User’s Manual
3.11.2.4 Port D (eSL and eSLZ000 only)
Port D Data Register
PORTD
Bit
DIR.
Description
Reset Value
PORTD
[7:0]
W
Port D output data Register
0x00
Port D Output Delay Control Register
PCOND
Bit
DIR.
Description
Reset Value
PCOND[0]
[0]
R/W
0:
Without delay
1:
Enable delay
0
3.11.3 Input Mode with Pull Up Resistor Delay Time
The data rise time in input mode with pull up resistor is 1.1µs. For example, the
input data is ready to access after 16 cycles in 16MHz without frequency
division as shown in the folowing example
:
R0 = #0XAAAA;
IO[PCON1B] = R0
IO[PCON2B] = R0
RPT #16
NOP
R1 = IO[PORTB]
3.11.4 I/O Port Application Examples
Figure 3-25a I/O Port - Driving an LED
(a) Bad design
(b) Good design
eSL
I/O
VDD
PB[0]
PB[1]
VDD
eSL
Содержание eSL Series
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