Elan eSL Series, Руководство пользователя

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Chapter 2
40
••••
Architecture eSL/eSLS Series (+ eSLZ000) User’s Manual
2.7 Oscillator System
The eSL Series oscillator system consists of an F
32k
RC/X’tal oscillator, internal
RC oscillator with a phase-locked loop (PLL) circuit, a clock select circuit, and
system clock dividers.
The Clock system architecture includes the basic frequency F
32K
, the PLL clock
frequency F
PLL
, and the system clock frequency F
SYS
.
The basic frequency F
32K
is used by eSL Series chips as multiplicand to obtain
F
PLL
CPU clock frequency, slow mode clock frequency, Real Time clock (RTC)
frequency, Watchdog counting frequency, and reset system warm up frequency.
The F
32K
frequency is 32KHz.
Likewise, the chips PLL clock frequency F
PLL
uses the basic frequency F
32K
as
multiplicand (see Section 2.7.2.2) to support frequencies used for Timer and
Pulse Width Modulation (PWM). Note that the F
SYS
also sources its frequency
from F
PLL
.
The system clock frequency F
SYS
,
(which uses F
PLL
as multiplicand to vary
frequencies to reduce power consumption) is used for CPU instruction clock
frequency selection and for Serial Peripheral Interface (SPI) TX and RX data
communication with eSL Series device and external flash or ROM. Take note
that the SPI function does not support eSLS.
ELAN eSL Series Oscillator System Attributes and Resources:
Item Resource
Clock source F
32K
, F
PLL
, F
SYS
Usage register FSR, SCS, SMC
I/O function pin OSCI, OSCO, OSCS, PLLC
2.7.1 Block Diagram
PLL
F
3 2K
F
PLL
F
SYS
Cl ock
Sw i tchi ng
Control
Circuit
System Cl ock
Di vi der
32.768kHz
RC/X'tal
OSC.
OSCI
OSCO
SCS FSR
F
PLL
OSCS
PLLC
F
32 K
SMC
F
32 K
Figure 2-18 ELAN eSL Series Oscillator System Block Diagram.