Embedded Solutions
Page 43 of 71
Reserved Registers – Offsets 0x020 -0x07F
Bit(s)
Description
Attribute Default
31:0
-
RO
0h
IP Control0 Register (IPx CR0)
IP0/IP1/IP2/IP3/IP4 - Offset 0x080/0x0E0/0x140/0x1A0
Bit(s)
Description
Attribute Default
31:19
Reserved
RO
0h
18
IP Reset* pin status
0 = IP Reset* is de-asserted (1), 1 = IP Reset* is asserted (0)
RO
0h
17
Reset IP and IP Channel
0 = Normal IP Reset* operation.
1 = IP Reset* is driven low and all IP channel related logic in
the FPGA is held in reset when this bit is set to 1. Upon writing
this bit back to zero, IP Reset* is de-asserted after the
expiration of that channels 256 millisecond reset counter to
ensure Reset* meets the 200ms minimum assertion time.
IP Reset* is always driven low when PCIe reset asserted.
R/W
0h
16
Reset IP
0 = Normal IP Reset* operation.
1 = Reset* is driven low when this bit is set to 1, upon writing
this bit back to zero, IP Reset* is de-asserted. Meeting the
minimum assertion time is the responsibility of the software. IP
Reset* is always driven low when PCIe reset asserted.
R/W
0h
15:14
Reserved
RO
0h
13
ACK* Activity Count enable
0 = ACK* Activity Counter disabled
1 = ACK* Activity Counter enabled
R/W
0h
12
Bus Error timeout select
0 = 127 IP Clocks – 4us @ 32MHz
0 = 63 IP Clocks – 8us @ 8MHz
1 = 255 IP Clocks – 8us @ 32MHz
1 = 127 IP Clocks - 16us @ 8MHz
R/W
0h
11:10
Reserved
RO
0h
9
IP Clock disable
0 = IP Clock enabled, 1 = IP Clock disabled
R/W
0h
8
Clock SEL
0 = 8MHz IP Clock
,
1 = 32MHz IP Clock
R/W
0h
7:0
See descriptions on next page for bits 7:0
-
-
