Dynamic Engineering PCIe3IP, Руководство пользователя

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Embedded Solutions
Page 8 of 71
Figure 1 PCIe3IP Block Diagram 14
Figure 2 PCIe3IP FPGA Block diagram 15
Figure 3 VPX2IP Base Address Map 18
Figure 4 PCIe3IP Base Address Map 19
Figure 5 PCIe5IP Base Address Map 20
Figure 6 PCIeIP Register Address Map 38
Figure 7 PCIeIP IP Logic Interface 52
Figure 8 PCIeIP IP I/O to 50 pin Header Connections 53
Figure 9 VPX2IP IP Carrier Rear IO Connector Assignment 54
Figure 10 PCIe3IP IP[2:0] I/O to 50 pin J[2:0] Header Diagram 57
Figure 11 VPX2IP IP[1:0] I/O to Condo Header or Rear IO (VPX) connector Diagram 64
List of Figures