Embedded Solutions
Page 44 of 71
IP Control0 Register (IPx CR0)
IP0/IP1/IP2/IP3/IP4 - Offset 0x080/0x0E0/0x140/0x1A0
Bit(s)
Description
Attribute Default
31:8
See descriptions on previous page for bits 31:8
-
-
7
Reserved
RO
0h
6:5
Increment Write Disable
-
Word Address Offset
Selects which 16-bit word is accessed on a 32bit or 64bit write
relative to the accesses address. Only has an effect when the
Address Increment Write Disable bit is asserted.
For 64 bit accesses
11 = Word3 is accessed four times.
10 = Word2 is accessed four times.
01 = Word1 is accessed four times.
00 = Word0 is accessed four times.
For 32 bit accesses
X1 = Word1 is accessed twice.
X0 = Word0 is accessed twice.
32 bit data accesses are required to be 32bit address aligned.
64 bit data accesses are required to be 64bit address aligned.
R/W
0h
4
Address Increment Write Disable
– For a 32 bit or 64bit PCI
Express write access each IP Write access uses the same
Word aligned address. The Word address used is specified
with the Increment Write Disable – Word Address Offset bits
(bits 6:5 above).
See Read version in IPx CR1
R/W
0h
3:2
Reserved
RO
0h
1
Word Swap
–
0 = Normal operation, 1 = Upper word is
swapped with lower word for each 32bit (Dword) transfer.
R/W
0h
0
Byte Swap
– 0 = Normal operation, 1= Byte 0 is swapped
with Byte1 for the first word & Byte 2 is swapped with byte 3
for the second word of a 32 bit transfer.
R/W
0h
