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VPX2IP IP Carrier Rear IO Connector Assignment – Option 2

VPX2IP IP Carrier I/O SMT to Rear IO Connections – Option 2 provides 32 differential pairs

IP[0] Connector/Pins

Pin Signal Names are named differentially as each

pair is routed to within .002” to enable up to 32

differential pairs

P0B

VPX_P2

VPX_BP

1 / 2

A1 / B1

IO0_0P / IO0_0N

3 / 4

D1 / E1

E1 / F1

IO0_1P / IO0_1N

5 / 6

B2 / C2

C2 / D2

IO0_2P / IO0_2N

7 / 8

E2 / F2

G2 / H2

IO0_3P / IO0_3N

9 / 10

A3 / B3

IO0_4P / IO0_4N

11 / 12

D3 / E3

E3 / F3

IO0_5P / IO0_5N

13 / 14

B4 / C4

C4 / D4

IO0_6P / IO0_6N

15 / 16

E4 / F4

G4 / H4

IO0_7P / IO0_7N

17 / 18

A5 / B5

IO0_8P / IO0_8N

19 / 20

D5 / E5

E5 / F5

IO0_9P / IO0_9N

21 / 22

B6 / C6

C6 / D6

IO0_10P / IO0_10N

23 / 24

E6 / F6

G6 / H6

IO0_11P / IO0_11N

25 / 50*

A7 / B7*

IO0_12P / IO0_12N

26 / 27

D7 / E7

E7 / F7

IO0_13P / IO0_13N

28 / 29

B8 / C8

C8 / D8

IO0_14P / IO0_14N

30 / 31

E8 / F8

G8 / H8

IO0_15P / IO0_15N

32 / 33

A9 / B9

IO0_16P / IO0_16N

34 / 35

D9 / E9

E9 / F9

IO0_17P / IO0_17N

36 / 37

B10 / C10

C10 / D10

IO0_18P / IO0_18N

38 / 39

E10 / F10

G10 / H10

IO0_19P / IO0_19N

40 / 41

A11 / B11

IO0_20P / IO0_20N

42 / 43

D11 / E11

E11 / F11

IO0_21P / IO0_21N

44 / 45

B12 / C12

C12 / D12

IO0_22P / IO0_22N

46 / 47

E12 / F12

G12 / H12

IO0_23P / IO0_23N

48 / 49

A13 / B13

IO0_24P / IO0_24N

*To meet differential routing tolerance IO[0]_12P/N are not consecutive

IP[1] Connector/Pins

Pin Signal Names are named differentially as each

pair is routed to within .002” to enable up to

32differential pairs

P1B

VPX_P2

VPX_BP

1 / 2

D13 / E13

E13 / F13

IO1_0P / IO1_0N

3 / 4

B14 / C14

C14 / D14

IO1_1P / IO1_1N

5 / 6

E14 / F14

G14 / H14

IO1_2P / IO1_2N

7 / 8

A15 / B15

IO1_3P / IO1_3N

9 / 10

D15 / E15

E15 / F15

IO1_4P / IO1_4N

11 / 12

B16 / C16

C16 / D16

IO1_5P / IO1_5N

13 / 14

E16 / F16

G16 / H16

IO1_6P / IO1

Notes: VPX_BP = VPX Back Plane side connectivity provided for user convenience; Module 1

IO can be swapped in place of IO from module 0 to balance signaling. See VPX2IP IP0/IP1
connectivity options section/diagram and/or contact Dynamic Engineering for customization

Figure 9 VPX2IP IP Carrier Rear IO Connector Assignment

Содержание PCIe3IP

Страница 1: ...sales dyneng com Est 1988 User Manual PCIeIP Carrier Series PCI Express x1 to IP Industry Pack Bridge Models in Group PCIe3IP Released PCIe5IP Released VPX2IP Released VPX4IP Coming soon Revision A1...

Страница 2: ...d S o l u t i o n s P a g e 2 o f 7 1 PCIe3IP PCI Express carrier with 3 IP positions Fab Number 10 2014 0202 3 FLASH Rev 0x10 PCIe5IP PCI Express carrier with 5 IP positions Fab Number 10 2015 1601 F...

Страница 3: ...E m b e d d e d S o l u t i o n s P a g e 3 o f 7 1 VPX2IP PCI Express carrier with 2 IP positions Fab Number 10 2016 1901 FLASH Rev 0x10...

Страница 4: ...improvements or changes in the product described in this document at any time and without notice Furthermore Dynamic Engineering assumes no liability arising out of the application or use of the devi...

Страница 5: ...IVITY MONITOR AND LOGIC 26 PCIEIP INTERRUPTS 28 PCIEIP REGISTERS 37 LED DECODE TABLE 49 PCIEIP BOARD FEATURES 52 PCIeIP Carrier IP Logic Connector Pin Assignment 52 PCIeIP IP Carrier IO Connector to 5...

Страница 6: ...LED s 60 PCIe5IP Board Revision 61 VPX2IP BOARD FEATURES 62 VPX2IP DIP Switches 62 VPX2IP LED s 63 VPX2IP IP0 IP1 connectivity options 64 VPX2IP Board Revision 65 MECHANICAL 66 APPLICATIONS GUIDE 66...

Страница 7: ...Embedded Solutions Page 7 of 71 For Service Contact 68 SPECIFICATIONS 69 ORDER INFORMATION 71...

Страница 8: ...e 5 PCIe5IP Base Address Map 20 Figure 6 PCIeIP Register Address Map 38 Figure 7 PCIeIP IP Logic Interface 52 Figure 8 PCIeIP IP I O to 50 pin Header Connections 53 Figure 9 VPX2IP IP Carrier Rear IO...

Страница 9: ...s fully compliant to PCI Express 1 1 revision of the PCI SIG specification and as such can operate in any compliant PCIe Gen1 Gen2 Gen3 or Gen4 slot Each IP position supports 8 16 bit IP devices and i...

Страница 10: ...ardless of the frequency of each clock the IP clock outputs are designed to be phase stepped in relation with one another to reduce simultaneous switching noise For the PCIe3IP and PCIe5IP the rising...

Страница 11: ...ERST is asserted Once PERST is de asserted each IP s clock starts toggling and each IP Reset will remain asserted until a 256ms timer expires Once the timer expires IP Reset de asserts synchronously w...

Страница 12: ...ition and mount into the system PCIeIP conforms to the VITA standard for IndustryPack Carriers This guarantees compatibility with multiple IndustryPack compatible modules Dynamic Engineering provides...

Страница 13: ...termination via CFG switches 8 User LED s 5 Power good indicator LED s an ACK activity LED for each IP Fused Filtered Power with resettable fuses for each position Windows Linux VxWorks drivers As Dyn...

Страница 14: ...Lattice ECP3 FPGA CFG TEST P5VGOOD Parallel CFG Data USER DIP Switch Inputs TDO PCIe REFCLK M12V P5V 3 3V 1 2V CFG TEST DIP Switch USER DIP Switch USER LED 7 0 x1 PCI Express Edge Fingers Connector T...

Страница 15: ...sor Receive Packet FIFO READ Completion Packet Generator Transmit Packet FIFO IP0 Channel IP Data Path State Machines Logic Register Rx Packet IP0 Rx Packet Tx Packet Interface Tx RDY Read Write Packe...

Страница 16: ...ined memory spaces 0xFFFF_FFFF is returned In all cases credits are updated If a packet is received with an address outside the PCIeIP s BAR0 space it is discarded credits are updated and an unsupport...

Страница 17: ...ated and sent to the core which will create Flow Control DLL packet s to inform update the Host that more space credit is available inside the PCIeIP For the VPX2IP PCIe3IP PCIe5IP there are three fou...

Страница 18: ...your own driver it is suggested to get the engineering kit and the Linux version of the SW Usually the code defines and perhaps some of the code can be reused in your effort VPX2IP Address Map Functio...

Страница 19: ...0x87F 128 Bytes IO Space IP1 0x880 to 0x8FF 128 Bytes IO Space IP2 0x900 to 0x97F 128 Bytes Reserved 0x980 to 0xBFF 640 Bytes INT Space IP0 0xC00 to 0xC7F 128 Bytes INT Space IP1 0xC80 to 0xCFF 128 B...

Страница 20: ...P3 0x980 to 0x9FF 128 Bytes IO Space IP4 0xA00 to 0xA7F 128 Bytes Reserved 0xA80 to 0xBFF 384 Bytes INT Space IP0 0xC00 to 0xC7F 128 Bytes INT Space IP1 0xC80 to 0xCFF 128 Bytes INT Space IP2 0xD00 to...

Страница 21: ...uch as the Switch and LED control may also be configured at this point Dynamic Drivers provide all of the above functionality and a generic IP driver for use when a specific IP driver is not available...

Страница 22: ...efore PERST is de asserted PCIeIP downloads the FPGA configuration file from a parallel Flash PERST signal is asserted and de asserted asynchronously IP Reset Summary Reset IPx_RESETN signal rules fro...

Страница 23: ...status IPx Control0 Register bit 18 Provides real time value of the IP s Reset pin state If 0 the IP Reset pin is de asserted 1 if 1 the IP Reset pin is asserted 0 P5VGOOD pin response If the PCIeIP...

Страница 24: ...32MHz oscillator clock on the PCIeIP board In order to reduce SSO Simultaneous Switching Outputs i e switching noise The PCIeIP has an IP Clock Phase Stepper circuit which phase shifts IP1 s clock ris...

Страница 25: ...eIP to do two 16bit IP transfers if ACK isn t received for the first 16bit IP transaction 0xFFFF_FFFF will be provided and the second 16bit IP transaction will not be generated on the IP bus If the AC...

Страница 26: ...erface write read cycles have completed which can be several ACK cycles when performing multi word accesses Note In the case of a Read Instruction the busy signal may go to the not busy state before t...

Страница 27: ...register bit 13 bit 1 2 Ensure each channels IP counter is clear by clearing IP0 IP1 and IP2 ACK Clear Enable bit by writing each channels IPx CTM bit 24 register bit 0 3 Instruct the software to sto...

Страница 28: ...ess has two possible types of Interrupt packets that can be generated they are INTx Legacy PCI Interrupt virtualization packets MSI Message Signal Interrupt packets PCIeIP supports both MSI and INTx i...

Страница 29: ...upt Pin Register offset 0x3D Interrupt Pin 7 0 RO register hardwired to 0x01 in PCIeIP to indicate INTA PCIeIP PCI Express MSI Interrupt Configuration Registers Summary Message Control Register offset...

Страница 30: ...bits each bit in this register can cause the generation of an Interrupt packet Interrupt Control Register ICR at offset 0x00C Contains bits that control the timing of when an interrupt packet is gene...

Страница 31: ...ed these bits are true high Each channel also has an IPx ICR register which contains an Interrupt enable bit for each source interrupt When disabled the interrupt source is Masked i e blocked from gen...

Страница 32: ...Interrupt de assertion time which ranges from 96 nanoseconds to 33 microseconds In most cases the edge mode will be used Level mode is useful when a device needs to be read or loaded whenever above be...

Страница 33: ...mber of interrupt sources that can cause PCIeIP to generate an interrupt packet to the Host depends upon how many IP s are connected Since there are 4 sources per IP the number of possible interrupt s...

Страница 34: ...ge monitoring circuit detects 5 volt power is out of specification it asserts the P5VGOOD pin to 0 Internally PCIeIP synchronizes the P5VGOOD pin value ensures it has been asserted for at least two cl...

Страница 35: ...s that reflect the IPx s IntReq 1 0 pin states after being synchronized inverted and filtered for 2 clocks Behavior Note Since the IPx Interrupt Request source bits IPx ISR bit 1 0 essentially reflect...

Страница 36: ...tion and Interrupt de assert timers when the system is in a quiescent state or if all ISR Interrupts have been processed and all Interrupts are disabled Masked by clearing all the IPx s ICR Interrupt...

Страница 37: ...errupt Control IP0 Interrupt Masks 0x90 Reserved Reserved for IP0 0x94 IP0 Transfer Monitor IP0 ACK Channel Transfer Activity Monitor 0x98 DF Reserved Reserved for IP0 Offset Register Description 0xE0...

Страница 38: ...trol 0x204 IP4 Control1 IP4 Channel behavior data flow control 0x208 IP4 Interrupt Status IP4 Interrupts 0x20C IP4 Interrupt Control IP4 Interrupt Masks 0x210 Reserved Reserved for IP4 0x214 IP4 Trans...

Страница 39: ...d Data Credits available from host 1101 Completion Data Credits available from host 1110 Scratch0 Register Value 1111 Scratch1 Register Value R W 0h 23 16 USER LED Control 7 0 0 off 1 on R W 0h 15 14...

Страница 40: ...3 Interrupts same as IP0 s RW1C 0h 11 8 IP2 Interrupts same as IP0 s RW1C 0h 7 4 IP1 Interrupts same as IP0 s RW1C 0h 3 IP0 Force P5VGOODn Interrupt Status 0 IP0 Force P5VGOODn Interrupt bit is not as...

Страница 41: ...s enabled when this timer expires INTA de assert packets are sent upon W1C of ISR occurrence 0000 32us 0100 512us 1000 8ms 1100 128ms 0001 64us 0101 1ms 1001 16ms 1101 256ms 0010 128us 0110 2ms 1010 3...

Страница 42: ...Bit s Description Attribute Default 31 0 Scratch1 register General purpose Read Writeable register for programming use Bits 7 0 may also be used to turn on LED s by setting their values to logic 1 an...

Страница 43: ...nsure Reset meets the 200ms minimum assertion time IP Reset is always driven low when PCIe reset asserted R W 0h 16 Reset IP 0 Normal IP Reset operation 1 Reset is driven low when this bit is set to 1...

Страница 44: ...ur times For 32 bit accesses X1 Word1 is accessed twice X0 Word0 is accessed twice 32 bit data accesses are required to be 32bit address aligned 64 bit data accesses are required to be 64bit address a...

Страница 45: ...ddress Only has an effect when the Address Increment Read Disable bit is asserted For 64 bit accesses 11 Word3 is accessed four times 10 Word2 is accessed four times 01 Word1 is accessed four times 00...

Страница 46: ...be set from the following two sources 1 User programmable interrupt set via this bit IPx Force IPx ISR bit 3 which provides the user a way to assert de assert an interrupt in a controlled fashion for...

Страница 47: ...pts section of the data sheet for further details Bit s Description Attribute Default 31 12 Reserved RO 0h 11 IPx Force P5VGOODn Interrupt Edge Level select 0 Edge Interrupt 1 Level Interrupt RW 0h 10...

Страница 48: ...ault 31 29 Reserved RO 0h 28 IPx Channel Busy 0 No transfers pending in IPx FIFO or channel 1 Indicates at least one transfer is still pending in the channel s FIFO or the IP interface is still proces...

Страница 49: ...g LED Signal Name Description LED 7 6 Always off LED 5 4 flash_sel 1 0 LED is on when switch pin is logic high 1 LED 3 Always off LED 2 0 fpga_sel 2 0 LED is on when switch pin is logic high 1 LED Sel...

Страница 50: ...its LED Signal Name Description LED 7 0 tx_ca_cplh 7 0 Completion Header Credits Host Completion header credits available i e provided from by host Actual Internal bus is 8 0 When 8 1 infinite credits...

Страница 51: ...0 When 12 1 infinite credits provided and all LED s turned on When 12 0 and any 11 8 1 all LED s are turned on except LED 0 LED Select 1110 Scratch0 Register offset 0x014 value LED Signal Name Descrip...

Страница 52: ...13 38 D10 A2 14 39 D11 n c Error 15 40 D12 A3 16 41 D13 IntReq0 17 42 D14 A4 18 43 D15 IntReq1 19 44 BS0 A5 20 45 BS1 n c Strobe 21 46 12V A6 22 47 12V ACK 23 48 5V n c Reserved 24 49 GND GND 25 50 N...

Страница 53: ...0 _12N 26 27 A26 A27 IO 2 0 _13P IO 2 0 _13N 28 29 A28 A29 IO 2 0 _14P IO 2 0 _14N 30 31 A30 A31 IO 2 0 _15P IO 2 0 _15N 32 33 A32 A33 IO 2 0 _16P IO 2 0 _16N 34 35 A34 A35 IO 2 0 _17P IO 2 0 _17N 36...

Страница 54: ...35 D9 E9 E9 F9 IO0_17P IO0_17N 36 37 B10 C10 C10 D10 IO0_18P IO0_18N 38 39 E10 F10 G10 H10 IO0_19P IO0_19N 40 41 A11 B11 A11 B11 IO0_20P IO0_20N 42 43 D11 E11 E11 F11 IO0_21P IO0_21N 44 45 B12 C12 C1...

Страница 55: ...age to be used to configure the FPGA at power up and can be read by reading the Switch and LED register 13 12 bits o SW2 5 3 are used to configure logic inside the FPGA These switch settings can be se...

Страница 56: ...when a single ACK assertion occurs The 1 2V 3 3V 5 0V 12 0V and 12 0V LED s are associated with their own independent voltage monitoring circuits which accurately detect if any of the board s voltages...

Страница 57: ...nected by default by stuffing or not stuffing resistor pads Please contact Dynamic Engineering if you desire a non default trace stuffing configuration IO0 24 0 P N R1 HDR_50 IP0 RT Angle Header With...

Страница 58: ...edded Solutions Page 58 of 71 PCIe3IP Board Revision The current PCIe3IP board revision is 10 2014 0203 At the release of this manual there are no known issues or Errata with this version of the PCIe3...

Страница 59: ...h image to be used to configure the FPGA at power up and can be read by reading the Switch and LED register 13 12 bits o SW2 5 is used to configure logic inside the FPGA This switch setting can be see...

Страница 60: ...is asserted on that channels IP bus Blinking logic is used to allow users to see when a single ACK assertion occurs The 1 2V 3 3V 5 0V 12 0V and 12 0V LED s are associated with their own independent...

Страница 61: ...kscreen has the following error TDO and TMS are swapped That is the TDO pin port is incorrectly labeled Silk Screened TMS and TMS is incorrectly labeled Silk Screened TDO o SW2 silkscreen has the foll...

Страница 62: ...to configure the FPGA at power up and can be read by reading the Switch and LED register 13 12 bits o SW2 5 3 are used to configure logic inside the FPGA These switch settings can be seen by reading t...

Страница 63: ...CK assertion occurs The 1 2V 3 3V 5 0V 12 0V and 12 0V LED s are associated with their own independent voltage monitoring circuits which accurately detect if any of the board s voltages are out of ran...

Страница 64: ...ion 1 Condo Header with Bezel no rear IO VPX_P2 R0 R3 are 0 ohm and R1 R2 R4 are open 3 Option 2 Rear IO no Condo Header with blank Bezel R1 R2 are 0 ohm and R0 R3 R4 are open a Standard Rear IO optio...

Страница 65: ...mbedded Solutions Page 65 of 71 VPX2IP Board Revision The current VPX2IP board revision is 10 2016 1901 At the release of this manual there are no known issues or Errata with this version of the VPX2I...

Страница 66: ...ready for use When installing the card the installer must be properly grounded and the hardware should be on an anti static work station Start up Make sure that the system can see your hardware before...

Страница 67: ...For high vibration environments inductors and other higher mass per joint components can be glued down Conformal Coating is an option For condensing environments conformal coating is required ROHS pr...

Страница 68: ...air charges must accompany the return Dynamic Engineering will not be responsible for damages due to improper packaging of returned items For service on Dynamic Engineering Products not purchased dire...

Страница 69: ...Drivers provide generic calls for GPB access to allow any user modification to be programmed with the standard driver Initialization Programming procedure documented in this manual Access Modes Regist...

Страница 70: ...d Solutions Page 70 of 71 User 8 position software readable switch 8 software controllable LED s 5 Power Supply indicator LED s IP activity LED s one for each IP 2 for VPX2IP 3 for PCIe3IP 5 for the P...

Страница 71: ...nt access INT and MSI interrupt support fused filtered power to the IP s local power supplies selectable 8 or 32 MHz operation per IP IP Debug Bus Provides test points on IP control signals power swit...

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