Embedded Solutions
Page 40 of 71
Reserved Register – Offsets 0x004
Bit(s)
Description
Attribute Default
31:0
-
RO
0h
Interrupt Status Register (ISR) – Offset 0x008
When any one or more of these interrupt bits are set an MSI or INTA# interrupt packet
will be generated and sent to the Host. The pre-masked source of these bits are
contained in the relative IPx Interrupt Status Register (i.e. IP0 ISR = 0x088). The Mask
bits for these bits are contained in the relative IPx Interrupt Control Register (i.e. IP0
ICR = 0x08C).
Bit(s)
Description
Attribute Default
If any of these bits/Interrupts are asserted an MSI will be sent to the system
31:20
Reserved
RO
0h
19:16
IP4 Interrupts same as IP0’s.
RW1C
0h
15:12
IP3 Interrupts same as IP0’s.
RW1C
0h
11:8
IP2 Interrupts same as IP0’s.
RW1C
0h
7:4
IP1 Interrupts same as IP0’s.
RW1C
0h
3
IP0 Force/P5VGOODn Interrupt Status
0 = IP0 Force/P5VGOODn Interrupt bit is not asserted or is
disabled/masked.
1 = IP0 Force/P5VGOODn Interrupt bit is asserted and is
enabled/unmasked.
RW1C
0h
2
IP0 Bus Error Interrupt Status
0 = IP0 Bus Error Interrupt not asserted or is
disabled/masked.
1 = IP0 Bus Error Interrupt asserted and enabled/unmasked.
RW1C
0h
1
IP0 IntReq1* Interrupt Status
0 = IP0 Interrupt pin not asserted or is disabled/masked.
1 = IP0 Interrupt pin asserted and enabled/unmasked.
*Note: Pin assertion is true low, bit value is the pin state
inverted.
RW1C
0h
0
IP0 IntReq0* Interrupt Status
0 = IP0 Interrupt pin not asserted or is disabled/masked.
1 = IP0 Interrupt pin asserted and enabled/unmasked.
*Note: Pin assertion is true low, bit value is the pin state
inverted.
RW1C
0h
