Embedded Solutions
Page 27 of 71
One possible usage example would be as follows:
A system engineer wants to issue and ensure completion of 20 Dword transfers
(composed of Reads and Writes) to IP0, then do and ensure completion of 20 Dword
transfers to IP1, then do and ensure completion of 20 Dword transfers to IP2. To do this
with the PCIeIP the engineer could do the following.
1) Enable each channels ACK* counter by setting each IP’s ACK* Count Enable
(IPx Control0 register bit [13]) bit = 1.
2) Ensure each channels IP counter is clear, by clearing IP0, IP1, and IP2 ACK*
Clear#/Enable bit by writing each channels IPx CTM bit [24] register bit = 0.
3) Instruct the software to stop issuing IP channel Read/Writes and then read each
IPx Channel Busy (IPx CTM bit [28]) indicator bit until each bit is 0.
4) Enable IP0, IP1, and IP2 ACK* counters to count their channel’s ACK*’s by
writing each channels IPx’s Clear#/Enable (IPx CTM bit [24]) register bit = 1.
5) Submit the 20 Dword transfers to IP0, then read IP0’s ACK* count value. When
the ACK* count is equal to 40 decimal all ACK* for the 20 Dword IP transfers
have been received.
6) Repeat 4) for IP1 then IP2.
