Dynamic Engineering PCIe3IP, Руководство пользователя

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Embedded Solutions
Page 39 of 71
Global/Board Level Registers - offsets 0x00 to 0x7F
Switch and LED register (SLR) – Offset 0x000
Bit(s) Description Attribute Default
31:28 Reserved RO 0h
27:24 LED Select
The decode selects summarize the LED settings. See the
LED Decode table for details of signals/status bits that drive
the PCIeIP LED’s for each setting.
0000 = Link and board status
0001 =
USER LED Control [7:0] – bits [23:16] of this register.
0010 = User switch settings – ‘1’ on pin turns on LED
0011 = FPGA/FLASH switch settings – ‘1’ turns on LED
0100 = IP0 Status
0101 = IP1 Status
0110 = IP2 Status
0111 = Reserved
1000 = Posted Header Credits – available from host
1001 = Non Posted Header Credits – available from host
1010 = Completion Header Credits – available from host
1011 = Posted Data Credits – available from host
1100 = Non Posted Data Credits – available from host
1101 = Completion Data Credits – available from host
1110 = Scratch0 Register Value
1111 = Scratch1 Register Value
R/W 0h
23:16 USER LED Control [7:0]
0 = off 1 = on
R/W 0h
15:14 Reserved RO 0h
13:12
FLASH Select [1:0] – Read Only bits that reflect SW2 [7:6]
switch settings. Since the factory default switch setting is
on/’1” these pins are pulled-up and seen as binary 2’b11.
The intent of these bits (switch settings) is to select PCIeIP
FPGA configuration/bit-map at boot-up. SW2 [7:6] = FLASH
Select [1:0] decodes. Currently only the 11 setting is
implemented and all switch settings load 11 map.
00 = 4K space with 1 PH/PD & 1 NPH/NPD credit.
01 = 4K space with 127 PH/PD & 32 NPH/NPD credits.
10 = 32MB space 1 PH/PD & 1 NPH/NPD credit.
11 = 32MB space with 127 PH/PD & 32 NPH/NPD credits.
RO 3h
11 Reserved RO 0h
10:8 FPGA Select [2:0] - TBD (No logic implemented at this time).
VPX2IP/PCIe3IP – Value read = SW2 [7:5] switch values.
PCIe5IP – Value read: bits[10:9] = 00, bit[8] = SW2 [5]
RO xh
7:0
User Switch values/settings
RO xh