Embedded Solutions
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PCIeIP Interrupt Functional Operation
The descriptions of the PCIeIP interrupt behavior to follow refer to the PCIe compliant
configuration registers and PCIeIP specific Interrupt registers both of which were
summarized in sections 1.0 and 2.0. This was done for the convenience of the reader
and should be sufficient for understanding the remainder of this document. For specific
details of PCIeIP Interrupt register bits/functions please refer to section 4.0. For PCI
Configuration register details please refer to the relevant PCI and/or PCIe specification.
When PCIeIP comes out of reset it is in INTA# mode as both the Interrupt Disable and
MSI Enable bits are 0 by default. It is up to the Host to determine if all devices in the
system can support MSI before configuring the system to use MSI Interrupts. This
section will first describe how PCIeIP INTA# virtualized signaling works then describe
the setup, functional, and behavioral differences for MSI Interrupts.
PCIeIP INTA# Interrupt Functional Operation
Each IP channel has 4 possible interrupt sources: Force/P5VGOODn, Bus Error, and
IntReq[1:0]*. The state of a channels interrupt sources are in its IPx ISR bits [3:0]. When
asserted these bits are true high. Each channel also has an IPx ICR register which
contains an Interrupt enable bit for each source interrupt. When disabled the interrupt
source is Masked (i.e. blocked) from generating an interrupt to the Host, each Interrupt
Enable/Mask bit is 0 by default (0 = disabled/masked). The Host may enable any IP
channel source interrupt independently by setting any of the IPx ICR [3:0] bits = 1.
If an Interrupt source is asserted and enabled (not Masked) it will be registered in the
ISR (0x008). The ISR has a register bit for every possible interrupt. When an ISR bit is
set it causes PCIeIP to generate and send a PCI Express INTA# Message packet that
contains an Assert INTA message code to the Host. Since PCIeIP only has one
interrupt for multiple possible interrupt sources the Host will have to read the ISR to
determine which Interrupt or Interrupts are asserted. To clear an Interrupt/bit the Host
must Write 1 to Clear (W1C) the interrupt bit in the ISR. When the Host executes a W1C
of an ISR bit or bits, the bit(s) will be cleared and PCIeIP will generate and send another
INTA# Message packet, this time the packet will contain a Deassert_INTA message
code.
Once a W1C of any ISR bit occurs the PCIeIP will wait until the Interrupt de-assert timer
expires before checking to see if an ISR bit is set. If an ISR bit is set when or after the
timer expires PCIeIP will generate another assert INTA# packet.
