Embedded Solutions
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Per the PCIe specification every access is at least a one long word. Byte, word, and
3byte accesses are supported utilizing PCIe byte enables. Any combination of byte
enables and starting address as defined by the PCIe specification is supported. The
PCIeIP supports PCIe transfer sizes of 1 and 2 long words (2Lwords = 1 quad word).
PCIe accesses are automatically converted into IP accesses and may range from a
single IP access up to 4 back-to-back IP accesses with the IP address incrementing
between cycles unless the address increment disable function is selected. For a read,
the IP read data is assembled, and a PCIe read completion packet is returned. The
Automatic generation of IP accesses greatly enhances the overall throughput when
transfers are > 2 bytes. Additionally, based on the PCIe byte enables the PCIeIP
determines when only a single 16 bit IP access needs to be performed for word or byte
transfers. In all cases the appropriate IP byte lane enables are applied as necessary.
Each IP clock is independently programmable for 8 or 32 MHz operation via a bit in its
control register. By default each IP CLK is 8MHz after power up and/or reset. The clock
frequency maybe changed at any time without consequence. Regardless of the
frequency of each clock, the IP clock outputs are designed to be “phase stepped” in
relation with one another to reduce simultaneous switching noise. For the PCIe3IP and
PCIe5IP the rising edge of IP1 clock is 8ns and IP2 clock is 16ns after the rising edge of
IP0’s clock. The PCIe5IP IP3/4’s clock is in phase with IP0/1’s clock. For the VPX2IP
the rising edge of IP1 clock is 8ns after the rising edge of IP0’s clock.
In normal operation IP access latency and performance is substantially better and the IP
logic runs 4 times faster when the IP CLK is 32MHz versus 8MHz.
PCIeIP has a programmable watchdog timer function, which completes the IP access if
the IP does not respond within the required amount of clock cycles. The watchdog timer
has a status bit and an optional Bus Error interrupt output.
PCIeIP supports interrupts from each IP slot with separate mask bits. Two interrupts
from each IP slot are supported. An interrupt force bit is available to aid in software
development in addition to the IP required 5V Power Good interrupt. All the interrupts
are maskable. The masked interrupt output signals are tied together and if asserted will
generate either MSI or INTA#.
PCIeIP has several programmable interrupt features to control when an interrupt is
generated. Programmable bits select behavior such as edge or level, or aggregation
timer values to pace the rate at which interrupts are generated (see Interrupt section for
details).
