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Service Manual PRELIMINARY
4.3.5
MCHK 660 IOD-Detected Failure (PCI Error)
The error log in Example 4–1 shows the following:
CPU 0 logged the error in a system with two CPUs.
The MCHK 660 register gives the reason for the Machine Check as an IOD
detected hard error or a Dtag Parity Error (if cached CPU)
The External Interface Status register records that the error occurred during
a D-ref Fill but does not indicate what the error is.
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The CAP Error register for IOD0 did not see an error.
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The CAP Error register for IOD1, however, records a serious PCI error.
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The MC Error Info registers 0 and 1 captured the error information.
The commander at the time of the error was CPU0 and the command was a
Read-I/O
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There is a PCI Subpacket from PCI1 with four nodes on it. Two devices on
the PCI bus did not see an error, however two did, the Mylex DAC960 and
the DEC_KZPSA. Either device could have caused the parity error.
Since this is an MCHK 660, the IOD-detected the error on the bus, and CPU0 is
logging the error. CPU0 registers are not important in this case since it is servicing
the IOD interrupt. There are three devices that can put data on the system bus:
CPUs, memory, or an IOD. The CAP Error register for IOD1 saw a serious error and
the MC Error Info register captured error information. See Section 4.4 for a
procedure designed to help with IOD-detected errors.
NOTE: The error log example has been edited to decrease its size; registers of
interest are in bold type. The “MC” bus is the system bus.
Refer to Table 4-9 for information on decoding commands, and refer to Table 4-10
for information on node IDs.
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