2-10
Table 2-2 lists the tests performed by the SROM.
Table 2-2 SROM Tests
Test Name
Logic Tested
D-cache RAM March
test
D-cache access, D-cache data, D-cache address logic
D-cache Tag RAM
March test
D-cache tag store RAM, D-cache bank address logic
S-cache Data March
test
S-cache RAM cells, S-cache data path, S-cache address
path
S-cache Tag RAM
March test
S-cache tag store RAM, S-cache bank address logic
I-cache Parity Error
test
I-cache parity error detection, ISCR register and error
forcing logic, IC_PERR_STAT register and reporting
logic
D-cache Parity Error
test
D-cache parity error detection, DC_MODE register and
parity error forcing logic, DC_PERR_STAT register and
reporting logic
S-cache Parity Error
test
S-cache parity error detection, AC_CTL register and
parity error forcing logic, SC_STAT register and
reporting logic
IOD Access test
Access to IOD CSRs, data path through CAP chip and
MDP0 on each IOD, PCI0 A/D lines <31:0>
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