5-12
Service Manual PRELIMINARY
Table 5-5 CAP Error Register
Name
Bits
Type
Initial
State
Description
MC_ERR VALID
<31>
RO
0
Logical OR of bits <30:23>
in this register. When set
MC_ERR0 and MC_ERR1
are latched.
RDSB
<30>
RW1C
0
Uncorrectable ECC error
detected by MDPB. Clear
state in MDPB before
clearing this bit.
RDSA
<29>
RW1C
0
Uncorrectable ECC error
detected by MDPA. Clear
state in MDPA before
clearing this bit.
CRDB
<28>
RW1C
0
Correctable ECC error
detected by MDPB. Clear
state in MDPB_STAT before
clearing this bit.
CRDA
<27>
RW1C
0
Correctable ECC error
detected by MDPA. Clear
state in MDPA_STAT before
clearing this bit.
NXM
<26>
RW1C
0
System bus master
transaction status NXM
(Read with Address bit <39>
set but transaction not pended
or transaction target above
the top of memory register.)
CPU will also get a fill error
on reads.
MC_ADR_PERR
<25>
RW1C
0
Set when a system bus
command/address parity error
is detected.
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