Digital Equipment AlphaServer 1200, Руководство по обслуживанию

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5-10 Service Manual PRELIMINARY
Table 5-4 MC Error Information Register 1
Name Bits Type
Initial
State
Description
VALID <31> RO 0 Logical OR of bits
<30:23> in the
CAP_ERR Register. Set
if MC_ERR0 and
MC_ERR1 contain a
valid address.
Reserved <30:21> RO 0
Dirty <20> RO 0 Set if the system bus
error was associated
with a Read/Dirty
transaction. When set,
the device ID field
<19:14> does not
indicate the source of
the data.
Reserved <19:17> All ones.
DEVICE_ID <16:14> RO 0 Slot number of bus
master at the time of the
error.
MC_CMD<5:0> <13:8> RO 0 Active command at the
time the error was
detected.
ADDR<39:32> <7:0> RO 0 Address bits <39:32> of
the transaction on the
system bus when an
error is detected.