DH Instruments PPCK PLUS, Руководство по эксплуатации и обслуживанию

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PPCK+™ Operation and Maintenance Manual
Page 109
©2001 DH Instruments, Inc .
Each of these status bits can cause a SRQ to occur. The Service Request Enable Register
(“
∗
SRE” program message ) determines which of these flags are able to assert the SRQ line.
This enable register has a matching set of bits that each will enable the designated bit to
cause a SRQ, except for the RQS/MSS bit(s) which cannot cause a SRQ. If you set this
register to 20 ($14 hex), an SRQ will occur if the MAV or the ERROR bit are set.
The description of these bits are given as:
•
OPER: N/A (Bit 7)
•
RQS: Requested Service (Bit 6)
Indicates that the SRQ line of the IEEE-488 interface has been asserted by the PPCK+.
This bit is cleared when a serial poll is performed on the PPCK+, and is a part of the
Status Byte Register when read using a serial poll. This bit does not apply if the COM1
port is being used.
•
MSS: Master Summary Status (Bit 6)
Indicates that an event or events occurred that caused the PPCK+ to request service
from the Host, much like the RQS bit. Unlike the RQS bit, it is READ ONLY and can be
only cleared when the event(s) that caused the service request are cleared.
•
ESB: Event Summary Bit (Bit 5)
Indicates if an enabled bit in the Standard Event Status Register became set (see
Section 4.5.3).
•
MAV: Message Available Bit (Bit 4)
Indicates that at least one reply message is waiting in the PPCK+ IEEE-488 output
queue.
•
ERROR: Error Queue not empty (Bit 2)
Indicates that at least one command error message is waiting in the PPCK+ IEEE-488
error message queue. Use the “ERR?” query to get this message.
•
RSB: Ready Summary Bit (Bit 0)
Indicates that an enabled bit in the Ready Status Register became set.