DFI EC510-SD, Руководство пользователя

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Chapter 5 Ports and Connectors
Chapter 5
USB 3-4 USB 3.0
USB 1-2 USB 3.0
J22
JP2 JP3
J21
HDMI (default)/DP
DVI
System
Fan 2
1
Front
Panel
5 1
2
1
10
9
1
1
1
1
4
SATA Power
-
DC-in
LAN 2
LAN 1
PCIe x16 (PCIE1)
SPI Flash
BIOS
VGA
Clear CMOS
Data (JP1)
Auto Power-on
Select (JP11)
(JP9)
1
6
(JP8) (JP15)
1
6
6
1
1
2 10
COM 3
1
(JP6)
6
6
9
1
2 10
COM 2
9
1
2
(JP7) (JP14)
6
6
1
2
1
2 10
COM 1
9
1
2
16
LPC
1
2
14
4-pin power
1
1
2
3 4
PCIe x4 (PCIE2)
Power
Button
Reset
DDR4_2 SODIMM
DDR4_1 SODIMM
1
(JP5)
6 6
1
1 1
6 6
2 2
2
6
1
4
Status LED
HDD LED
2
25
26
Parallel
1
DIO Power
DIO
S/PDIF
Front Audio
2
5 1
1
10
9
ECX
+
SATA 3.0
USB 2.0 13-14
(JP13)
1
1
(JP12)
1
SATA 0
SATA 1
1
Mini PCIe
mSATA System
Fan 1
1
1
bettery
1
1
1
2 12
USB 2.0 9
USB 3-4 USB 3.0
USB 1-2 USB 3.0
J22
JP2
JP3
J21
HDMI (default)/DP
DVI
System
Fan 2
1
Front
Panel
5 1 2
1
10
9
1
1
1
1
4
SATA Power
-
DC-in
LAN 2
LAN 1
PCIe x16 (PCIE1)
SPI Flash
BIOS
VGA
Clear CMOS
Data (JP1)
Auto Power-on
Select (JP11)
(JP9)
1
6
(JP8) (JP15)
1
6
6
1
1
2 10
COM 3
1
(JP6)
6
6
9
1
2 10
COM 2
9
1
2
(JP7) (JP14)
6
6
1
2
1
2 10
COM 1
9
1
2
16
LPC
1 2
14
4-pin power
1
1
2
3 4
PCIe x4 (PCIE2)
Power
Button
Reset
DDR4_2 SODIMM
DDR4_1 SODIMM
1
(JP5)
6
6
1
1 1
6
6
2 2
2
6
1
4
Status LED
HDD LED
2
25
26
Parallel
1
DIO Power
DIO
S/PDIF
Front Audio
2
5 1
1
10
9
ECX
+
SATA 3.0
USB 2.0 13-14
(JP13)
1
1
(JP12)
1
SATA 0
SATA 1
1
Mini PCIe
mSATA System
Fan 1
1
1
bettery
1
1
1
2 12
USB 2.0 9
S/PDIF Connector
1 5
+5V
Key
SPDIF out
Ground
SPDIF in
S/PDIF
The S/PDIF connector is an audio interface for transmitting digital audio signals. The system
includes an S/PDIF header on the mainboard. Make sure pin 1 of the audio cable is aligned
with pin 1 of the S/PDIF connector.
LPC Connector
LPC
The Low Pin Count Interface was defined by Intel
®
Corporation to facilitate the industry’s transi-
tion towards legacy free systems. It allows the integration of low-bandwidth legacy I/O compo-
nents within the system, which are typically provided by a Super I/O controller. Furthermore, it
can be used to interface firmware hubs, Trusted Platform Module (TPM) devices and embedded
controllers. Data transfer on the LPC bus is implemented over a 4 bit serialized data interface,
which uses a 24MHz LPC bus clock. For more information about LPC bus, please refer to the
Intel
®
Low Pin Count Interface Specification Revision 1.1’. The table below indicates the pin
functions of the LPC connector.
Pin Pin Assignment Pin Pin Assignment
1
L_CLK
2
L_AD1
3
L_RST#
4
L_AD0
5
L_FRAME#
6
3V3
7
L_AD3
8
GND
9
L_AD2
10
Kev
11
INT_SERIRQ
12
GND
13
5VSB
14
5V
1
2
13
14