EPIQ 5 & 7 Training Manual
© 2016 Conquest Imaging
5
These processing functions include reconstruction of the transmit
beam, quadrature bandpass filtering, frequency compounding, log
detection, sample rate conversion, phase detection, color
packetization and Doppler range gating.
Aquistion Control Board Block Diagram
The FPGAs are clocked at 80MHz which is supplied by the Channel
Board. There is also an on-board 80 MHz backup clock that
automatically takes over in the event the CB clock is not present.
The ACB receives the PCIe clock from the motherboard along with
control panel input/transducer receive data. It uses the PCIe bus to
pass information between the ACB and the motherboard.
The Argon FPGA controls the transmission sequence by sending the
Xmit Start signal to the CB. Argon also provides the master clock of
the I
2
C bus. The main function of the I
2
C bus in this system is ambient
temperature management. Ambient temperature is monitored near
all FPGAs, CPUs and the power regulator board. It communicates with
the four other PIC processors that monitor temperature located on
the following boards:
ACB
Xenon
Argon
CB
I
2
C
80 MHz Clock
Thermistor
I
2
C
Summed RF data
Estimated data
Scan DMA
CTRL Logic
BP/Host Control
COMM DMA
Scan DMA
Acoustic DMA
PCIe
Test
Pins &
LEDs
Logic Voltage
Generation
+9V Neon1
+9V Neon0
+12V
PIC
Motor cntrl
I
2
C
To BP
12VDC
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