CMOSTEK CMT2380F17, Руководство пользователя

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CMT2380F17
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The SPI in CMT2380F17 is double buffered data both in the transmit direction and in the receive direction.
New data for transmission cannot be written to the THR until the THR is empty. The read-only flag, THRF,
indicates the THR is full or empty. The WCOL (SPSTAT.6) bit is set to indicate data collision when the data
register is written during set THRF. In this case, the SPDAT writing operation is ignored.
While write collision is detected for a master or a slave, it is uncommon for a master because the master
has full control of the transfer in progress. The slave, however, has no control over when the master will
initiate a transfer and therefore collision can occur.
WCOL can be cleared in software by writing ‘1’ to the bit.
20.2.6 SPI Clock Rate Select
The SPI clock rate selection (in master mode) uses the SPR1 and SPR0 bits in the SPCON register and
SPR2 in the SPSTAT register, as shown in Table 20
–2.
Table 20-2. SPI Serial Clock Rates
SPR2 SPR1 SPR0
SPI Clock
Selection
SPI Clock Rate @
SYSCLK=12MHz
SPI Clock Rate @
SYSCLK=48MHz
0 0 0 SYSCLK/4 3 MHz 12 MHz
0 0 1 SYSCLK/8 1.5 MHz 6 MHz
0 1 0 SYSCLK/16 750 KHz 3 MHz
0 1 1 SYSCLK/32 375 KHz 1.5 MHz
1 0 0 SYSCLK/64 187.5 KHz 750 KHz
1 0 1 SYSCLK/2 6 MHz 24 MHz
1 1 0 S0TOF/6 Variable Variable
1 1 1 T0OF/6 Variable Variable
Note
：
1. SYSCLK is the system clock.
2. S0TOF is UART0 Baud-Rate Generator Overflow.
3. T0OF is Timer 0 Overflow.
。