CMOSTEK CMT2380F17, Руководство пользователя

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CMT2380F17
Rev0.1 | 21/347
www.cmostek.com
1.18 Controller Serial Port Timing Characteristics
Parameter Symbol Condition
URM0X3 = 0 URM0X3 = 1 Unit
Min. Max. Min. Max.
Serial Port Clock Cycle Time t
XLXL
12T 4T T
SYSCLK
Output Data Setup to Clock Rising Edge t
QVXH
10T-20 2T-20 ns
Output Data Hold after Clock Rising Edge t
XHQX
T-10 T-10 ns
Input Data Hold after Clock Rising Edge t
XHDX
5 5 ns
Clock Rising Edge to Input Data Valid t
XHDV
2T-10
2T-10
ns
VALID VALID VALID VALID VALID VALID VALID VALID
1 2 3 4 5 6 7 0
t
XHQX
SET RI
SET TI
WRITE TO SBUF
OUTPUT DATA
CLEAR RI
INPUT DATA
CLOCK
t
XHDX
t
XLXL
t
QVXH
t
XHDV
Figure 1-1. Shift Register Mode Timing Waveform
1.19 Controller SPI Timing Characteristics
Parameter Symbol Condition Note Typ. Max. Unit
SPICLK High Time
t
MCKH
Master mode
timing
1T T
SYSCLK
SPICLK Low Time
t
MCKL
1T T
SYSCLK
MISO Valid to SPICLK Sample Edge
t
MIS
10 ns
SPICLK Shift Edge to MISO Change
t
MIH
0 ns
SPICLK Shift Edge to MOSI Change
t
MOH
10 ns
nSS Falling to First SPICLK Edge
t
SE
Slave mode
timing
2T T
SYSCLK
Last SPICLK Edge to nSS Rising
t
SD
2T T
SYSCLK
nSS Falling to MISO Valid
t
SEZ
4T T
SYSCLK
nSS Rising to MISO High-Z
t
SDZ
4T T
SYSCLK
SPICLK High Time
t
CKH
2T T
SYSCLK
SPICLK Low Time
t
CKL
2T T
SYSCLK
MOSI Valid to SPICLK Sample Edge
t
SIS
1T T
SYSCLK
SPICLK Sample Edge to MOSI Change
t
SIH
1T T
SYSCLK
SPICLK Shift Edge to MISO Change
t
SOH
2T T
SYSCLK
Last SPICLK Edge to MISO Change
(CPHA = 1 ONLY)
t
SLH
1T 2T T
SYSCLK