CMOSTEK CMT2380F17, Руководство пользователя

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CMT2380F17
Rev0.1 | 38/347
www.cmostek.com
Figure 4-4. Receive Signal Jump Diagram
PJD identifies an input signal transition from 0 to 1 or from 1 to 0 as a phase jump. Users simply configure
PJD_WIN_SEL<1:0> to indicate PJD how many signal transitions need to be detected before output the judgment result. As
shown in above diagram, 6 phase jumps occurred among the total of 8 symbols received, meaning the jump number is not equal
to the number of symbols. The jump count is equivalent to the number of symbols only if preamble is received. In general, the
more signal transition detected, the more reliable the judgment is. The less, the faster the detection completes. If the receiving
time window is small, the number of detections needs to be reduced to meet the window setting requirements. In general, 4 signal
transitions detection can ensure reliable detection, that is, neither misjudging noise as a useful signal nor the detection failure of a
useful signal will happen.
Monitoring signal transitions is essentially monitoring whether the signal meets the expected data rate, meanwhile, the PJD
also automatically monitors whether the error of the signal meets the agreed value of the valid signal and determines if the SNR
exceeds 7 dB. It outputs 1 if it determines a reliable signal is received based on the combined data rate, error and SNR
monitoring results, otherwise it outputs 0 if it determines the signal is noise or interference signal. This result can be output to the
RSSI VLD interrupt or to the implementation instance of the internal assisting super-low power (SLP) receive mode. In the direct
mode, the FSK demodulation output can also be muted through setting the DOUT_MUTE register bit to 1based on phase jump
detect result.
PJD is similar to traditional carrier sense(CS) technique, more reliable though. A combine of RSSI monitoring and PJD
technique ensures accurate channel state identification.
4.9 Receiver Clock Data Recovery (CDR)
CDR system is largely to recover the clock signal synchronized with the data rate while receiving data, either for decoding
inside the chip or outputting to the GPIO for users to sample data. Error existing between the recovered clock frequency and the
actual transmitted data rate will cause data acquisition errors, error codes and decoding errors during data reception. Therefore,
CDR takes a simple but critical role.
The CMT2380F17 receiver supports three CDR systems according to different application requirements:

COUNTING system
This system is designed for the case where the data rate is relatively accurate. If the data rate is 100% aligned, users can
even receive unlimited lengths of
0 without error.

TRACING system
This system is designed for dealing with large data rate errors. It has a tracking function that automatically detects the data
rate transmitted by TX and adjusts the RX local data rate promptly to minimize the error between them. This system leads
the industry by supporting up to 15.6% error.

MANCHESTER system
This system comes from COUNTING system by inheriting its basic features except a difference on specific design for
Manchester codec, which performs special treatment in case of a sudden change in the TX data rate to identify the signal
part with sudden changes.