CMOSTEK CMT2380F17, Руководство пользователя, Страница: 224 / 347

CMT2380F17
Rev0.1 | 224/347
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0: Must be cleared by software.
1: Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time in the
other modes, in any serial reception (except see SM20).

S0BUF
：
Serial port 0 Buffer Register
SFR Page = 0 only
SFR Address = 0x99
Bit
7 6 5 4 3 2 1 0
Name
S0BUF[7:0]
R/W
R/W R/W R/W R/W R/W R/W R/W R/W
Reset Value
X X X X X X X X
Bit 7~0: It is used as the buffer register in transmission and reception.

SADDR
：
Slave Address Register
SFR Page = 0~F
SFR Address = 0xA9
Bit 7 6 5 4 3 2 1 0
Name SADDR[7:0]
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset Value 0 0 0 0 0 0 0 0

SADEN
：
Slave Address Mask Register (SMOD3 = 0)
SFR Page = 0~F
SFR Address = 0xB9
Bit 7 6 5 4 3 2 1 0
Name SADEN[7:0]
R/W
R/W R/W R/W R/W R/W R/W R/W R/W
Reset Value
0 0 0 0 0 0 0 0
SADDR register is combined with SADEN register to form Given/Broadcast Address for automatic
address recognition. In fact, SADEN functions as the “mask” register for SADDR register. The following is the
example for it.
SADDR = 1100 0000
SADEN = 1111 1101
Given = 1100 00x0 The Given slave address will be checked
except
bit 1 is treated as “don’t care”
The Broadcast Address for each slave is created by taking the logical OR of SADDR and SADEN. Zero in
this result is considered as “don’t care”. Upon reset, SADDR and SADEN are loaded with all 0s. This
produces a Given Address of all “don’t care” and a Broadcast Address of all “don’t care”. This disables the
automatic address detection feature.

PCON0
：
Power Control Register 0
SFR Page = 0~F
SFR Address = 0x87 POR = 0001-0000, RESET = 0000-0000
Bit 7 6 5 4 3 2 1 0
Name SMOD1 SMOD0 GF POF GF1 GF0 PD IDL
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset Value 0 0 0 0 0 0 0 0
Bit 7: SMOD1, double Baud rate control bit. 0: Disable double Baud rate of the UART.
1: Enable double Baud rate of the UART in mode 1, 2, or 3.