CMOSTEK CMT2380F17, Руководство пользователя

Страница: 174 / 347

CMT2380F17
Rev0.1 | 174/347
www.cmostek.com
and low bytes of the count values), CHRL, CLRL (the high and low bytes reload registers), as shown in Figure
17
–2. CHRL and CLRL are reloaded to CH and CL at each time overflow on {CH+CL} counter which can
change the PCA cycle time for variable PWM resolution, such as 7-bit or 9-bit PWM.
{CH + CL} is the common time base for all modules and its clock input can be selected from the following
source:
•
1/12 the system clock frequency,
•
1/2 the system clock frequency,
•
The Timer 0 overflow, which allows for a range of slower clock inputs to the timer,
•
External clock input, 1-to-0 transitions, on ECI pin,
•
CKMIX16, refer Section “9.1 Clock Structure”,
•
Directly from the system clock frequency,
•
The S0BRG overflow, S0TOF,
•
MCKDO, refer Section “9.1 Clock Structure”.
Special Function Register CMOD contains the Count Pulse Select bits (CPS2, CPS1 and CPS0) to
specify the PCA timer input. When CPS[2:0] indexes CKMIX16 or MCKDO, the frequency of the input
clock sources must
≥
CPUCLK x3 and
≥
SYSCLK x2.This register also contains the ECF bit which
enables an interrupt when the counter {CH+CL} overflows. And the counter overflow toggles C0COR, it
will output on port pin when C0CKOE is enabled. In addition, the user has the option of turning off the PCA
timer during Idle Mode by setting the Counter Idle bit (CIDL). This can further reduce power consumption
during Idle mode.
Figure 17-2. PCA Timer/Counter