CMT2380F17
Rev0.1 | 39/347
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4.10
Fast Manual Frequency Hopping
Manual frequency hopping refers to switching an original basic frequency point obtained by RRPDK configuration, e.g.
433.92MHz,to another frequency point by simply setting 1 or 2 registers on MCU during the application, which simplify user's
operation much for switching frequency points frequently in multi-channel applications.
General processing steps follow: 1) Set FH_OFFSET<7:0> during the initialization configuration of power-up. 2) Switch
channels constantly as desired in the application by changing FH_CHANNEL<7:0>.
When fast manual frequency hopping in the receiving mode is performed, it needs to have special process on AFC
parameters. Please refer to
AN197-CMT2300A-CMT2119B-CMT2219B Fast Manual Frequency Hopping
and
CMT2300
as well
as
CMT2219B Frequency Hopping Calculation Table
for more details.
4.11
Transceiver Control Interface and Operating Mode
4.11.1
Transceiver SPI Interface Timing
The RF system of CMT2380F17 communicates with the controller section via a 4-wire SPI port (FCSB, CSB, SDA and
SCLK). The low active CSB is the chip selection signal used to access the registers. The low active FCSB is the chip selection
signal used to access the FIFO. The above two cannot be set to low both at the same time. SCLK is a serial clock with speed up
to 5MHz.Data is sent on the falling edge of SCLK and collected on the rising edge for the chip itself or an external MCU. SDA is a
bidirectional pin for inputting and outputting data. Both the address and data parts are transmitted from the MSB.
The CSB is pulled low when registers are accessed. An R/W bit followed by a 7-bit register address is sent. After the
controller pulls CSB low, it must wait for at least half a SCLK cycle before it can start transmitting R/W bits. After the controller
sends the falling edge of the last SCLK, it must wait for at least half of the SCLK cycle before pulling CSB high.
It should be noted that, as for read register operations, both the controller and the transceiver may generate a switch IO
(SDA) port event among address 0 and data 7. At this point, SDA will switch the IO port from input to output, and the controller will
switch the corresponding IO port from output to input. In the below figure, please notice the position of the dotted line in the
middle, at this time, it is strongly recommended the controller switches the IO port to input before it sends the falling edge of
SCLK. The transceiver will switch the IO to output after it receives the falling edge, which avoids situations where the both set
SDA to output resulting in electrical conflicts.
SCLK
CSB
SDA
X
0
1
2
3
4
5
6
7
X
register address
register read data
0
1
2
3
4
5
6
7
r/w = 1
FCSB
> 0.5 SCLK cycle
> 0.5 SCLK cycle
Figure 4-5. Transceiver SPI Read Register Timing
Содержание CMT2380F17
Страница 27: ...CMT2380F17 Rev0 1 27 347 www cmostek com 1 25 Phase Noise...
Страница 111: ...CMT2380F17 Rev0 1 111 347 www cmostek com INT2IS 1 0 Selected Port Pin of nINT2 00 P4 4 01 P3 0 10 P1 1 11 P1 6...
Страница 131: ...CMT2380F17 Rev0 1 131 347 www cmostek com Figure 16 1 Timer 0 Mode 0 Structure Figure15 2 Timer 1 Mode 0 Structure...
Страница 161: ...CMT2380F17 Rev0 1 161 347 www cmostek com Figure 16 32 Split Timer 3 Mode 1 Structure AR with Ex INT...
Страница 177: ...CMT2380F17 Rev0 1 177 347 www cmostek com Figure 17 3 PCA Interrupt System...
Страница 239: ...CMT2380F17 Rev0 1 239 347 www cmostek com Figure 19 5 8 bit Timer Mode Configuration for S1BRG S1TME 1...
Страница 246: ...CMT2380F17 Rev0 1 246 347 www cmostek com SnMIPS S0MI S1MI 1 P3 3 P4 7...
Страница 289: ...CMT2380F17 Rev0 1 289 347 www cmostek com...
