CMOSTEK CMT2380F17, Руководство пользователя, Страница: 68 / 347

CMT2380F17
Rev0.1 | 68/347
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9 System Clock
There are three clock sources for the system clock: Internal High-frequency RC Oscillator (IHRCO),
Internal Low-frequency RC Oscillator (ILRCO) and External Clock Input. Figure 9
–1 shows the structure of the
system clock in CMT2380F17.
The CMT2380F17 always boots from IHRCO on 12MHz. Software can select the OSCin input on one of
the three clock sources application required and switches them on the fly. But software needs to settle the
clock source stably before clock switching. In external clock input mode (ECKI), the clock source comes from
P6.0 input.
The built-in IHRCO provides two kinds of frequency for software selected. Another frequency is
11.059MHz by software setting AFS on CKCON0.7. Both of 12MHz and 11.059 MHz in IHRCO provide high
precision frequency for system clock source. To find the detailed IHRCO performance, please refer Section
“33.4 IHRCO Characteristics”). In IHRCO or ILRCO mode, P6.0 can be configured to internal MCK output or
MCK/2 and MCK/4 for system application.
The built-in ILRCO provides the low power and low speed frequency about 32KHz to WDT and system
clock source. MCU can selects the ILRCO to system clock source by software for low power operation. To find
the detailed IHRCO performance, please refer Section “33.5 ILRCO Characteristics”). In ILRCO mode, P6.0
can be configured to internal MCK output or MCK/2 and MCK/4 for system application.
The CMT2380F17 device includes a Clock Multiplier (CKM) to generate the high speed clock for system
clock source. CKM applied in CMT2380F17 is shown in Figure 9
–1 and its typical input frequency is around
6MHz. Before enable CKM, software must configure the CKMIS1~0 (CKCON.5~4) to get the reasonable
CKMI frequency for CKM input source. CKM can generate 4/5.33/8 times frequency of CKMI and setting
MCKS1~0 (CKCON2.3~2) selects different CKM outputs to provide the high speed operation on MCU without
high-
frequency clock source. To find the detailed CKM performance, please refer Section “33.6 CKM
Characteristics”).
The system clock, SYSCLK, is obtained from one of these four clock sources through the clock divider, as
shown in Figure 9
–1. The user can program the divider control bits SCKS2~SCKS0 (in CKCON0 register) to
get the desired system clock.
。
9.1 Clock Structure
Figure 9
–1 presents the principal clock systems in the CMT2380F17. The initial oscillator source of
CPUCLK is set to IHROC 12MHz. It can use the combinations of the clock multiplier and divider for different
frequencies. The maximum CPUCLK is as following:
-
External clock input mode: Up to 12MHz @ 2.0V
– 5.5V; Up to 25MHz @ 2.4V – 5.5V
-
CPU up to 12MHz @ 1.8V
– 5.5V; Up to 25MHz @ 2.2V – 5.5V
-
CPU up to 36MHz @ 2.7V -5.5V with on-chip CKM
If the applications need higher performance, then HSE (DCON0 Bit 7) needs to be set when CPUCLK >
6MHz. Moreover, if needs ultra-high CPUCLK>25MHz, then HSE1 needs to be set.
The system clock can be sourced by the external oscillator circuit or either internal oscillator. It maximum