AXIOMTEK STX88810VEA, Руководство пользователя

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STX88810 STX Evaluation Platform Module Series User’s Manual
Award BIOS Utility
43
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DRAM Data Integrity Mode
This option sets the data integrity mode of the DRAM installed in the
system. The default setting is
“Non-ECC”
.
z
System BIOS Cacheable
Selecting Enabled allows caching of the system BIOS ROM at F0000h-
FFFFFh, resulting in better system performance. However, if any program
writes to this memory area, a system error may result. The default value
is
“Disabled”
.
z
Video BIOS Cacheable
This item allows you to change the Video BIOS location from ROM to
RAM. Video Shadow will increase the video speed.
z
Video RAM Cacheable
Selecting Enabled allows caching of the video BIOS ROM at C0000h to
C7FFFh, resulting in better video performance. However, if any program
writes to this memory area, a system error may result. The default value
is
“Disabled”
.
z
Memory Hole at 15M-16M
You can reserve this area of system memory for ISA adapter ROM.
When this area is reserved, it cannot be cached. The user information of
peripherals that need to use this area of system memory usually
discusses their memory requirements. The default value is
“Disabled”
.
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Delayed Transaction
The chipset has an embedded 32-bit posted write buffer to support delay
transactions cycles. Select
Enabled
to support compliance with PCI
specification version 2.1. The options available are
Enabled
and
Disabled
.
z
AGP Aperture Size (MB)
The field sets aperture size of the graphics. The aperture is a portion of
the PCI memory address range dedicated for graphics memory address
space. Host cycles that hit the aperture range are forwarded to the AGP
without any translation. The options available are 4M, 8M, 16M, 32M,
64M, 128M and 256M.