Atmel SAM9X25, Руководство пользователя

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page 452 ) and performing a write access at any location in the low-power DDR1-
SDRAM to acknowledge this command.
9. Perform a write access to any low-power DDR1-SDRAM address.
10. Write the refresh rate into the count field in the DDRSDRC Refresh Timer register (see
page 453 ). (Refresh rate = delay between refresh cycles). The low-power DDR1-
SDRAM device requires a refresh every 15.625 μs or 7.81 μs. With a 100 MHz fre-
quency, the refresh timer count register must to be set with (15.625*100 MHz) = 1562
i.e. 0x061A or (7.81*100 MHz) = 781 i.e. 0x030d
11. After initialization, the low-power DDR1-SDRAM device is fully functional.
30.4.3 DDR2-SDRAM Initialization
The initialization sequence is generated by software. The DDR2-SDRAM devices are initialized
by the following sequence:
1. Program the memory device type into the Memory Device Register (see Section 30.7.8
on page 463 ).
2. Program the features of DDR2-SDRAM device into the Timing Register (asynchronous
timing (trc, tras, etc.)), and into the Configuration Register (number of columns, rows,
banks, cas latency and output drive strength) (see
Section 30.7.3 on page 454 , Section
30.7.4 on page 457 and Section 30.7.5 on page 459 ).
3. An NOP command is issued to the DDR2-SDRAM. Program the NOP command into
the Mode Register, the application must set Mode to 1 in the Mode Register (see
Sec-
tion 30.7.1 on page 452 ). Perform a write access to any DDR2-SDRAM address to
acknowledge this command. Now clocks which drive DDR2-SDRAM device are
enabled.
A minimum pause of 200 μs is provided to precede any signal toggle.
4. An NOP command is issued to the DDR2-SDRAM. Program the NOP command into
the Mode Register, the application must set Mode to 1 in the Mode Register (see
Sec-
tion 30.7.1 on page 452 ). Perform a write access to any DDR2-SDRAM address to
acknowledge this command. Now CKE is driven high.
5. An all banks precharge command is issued to the DDR2-SDRAM. Program all banks
precharge command into the Mode Register, the application must set Mode to 2 in the
Mode Register (See
Section 30.7.1 on page 452 ). Perform a write access to any DDR2-
SDRAM address to acknowledge this command
6. An Extended Mode Register set (EMRS2) cycle is issued to chose between commer-
cial or high temperature operations. The application must set Mode to 5 in the Mode
Register (see
Section 30.7.1 on page 452 ) and perform a write access to the DDR2-
SDRAM to acknowledge this command. The write address must be chosen so that
BA[1] is set to 1 and BA[0] is set to 0. For example, with a 16-bit 128 MB DDR2-
SDRAM (12 rows, 9 columns, 4 banks) bank address, the DDR2-SDRAM write access
should be done at the address 0x20800000.
Note: This address is for example purposes only. The real address is dependent on implementation in
the product.
7. An Extended Mode Register set (EMRS3) cycle is issued to set the Extended Mode
Register to “0”. The application must set Mode to 5 in the Mode Register (see
Section
30.7.1 on page 452 ) and perform a write access to the DDR2-SDRAM to acknowledge
this command. The write address must be chosen so that BA[1] is set to 1 and BA[0] is
set to 1. For example, with a 16-bit 128 MB DDR2-SDRAM (12 rows, 9 columns, 4
banks) bank address, the DDR2-SDRAM write access should be done at the address
0x20C00000.