Atmel SAM9X25, Руководство пользователя

Страница: 488 / 1145

488
11054A–ATARM–27-Jul-11
SAM9X25
488
11054A–ATARM–27-Jul-11
SAM9X25
Channel Enable in the Channel Status Register (DMAC_CHSR.ENABLE[n]) until it is
disabled, to detect when the transfer is complete. If the DMAC is not in Row 1, the next
step is performed.
6. The DMAC transfer proceeds as follows:
a. If interrupts is un-masked (DMAC_EBCIMR.BTC[x] = ‘1’, where x is the channel
number) hardware sets the buffer complete interrupt when the buffer transfer has
completed. It then stalls until the STALLED[n] bit of DMAC_CHSR register is
cleared by software, writing ‘1’ to DMAC_CHER.KEEPON[n] bit where n is the
channel number. If the next buffer is to be the last buffer in the DMAC transfer, then
the buffer complete ISR (interrupt service routine) should clear the automatic mode
bit in the DMAC_CTRLBx.AUTO bit. This put the DMAC into Row 1 as shown in
Table 31-3 on page 479 . If the next buffer is not the last buffer in the DMAC trans-
fer, then the reload bits should remain enabled to keep the DMAC in Row 4.
b. If the buffer complete interrupt is masked (DMAC_EBCIMR.BTC[x] = ‘1’, where x is
the channel number), then hardware does not stall until it detects a write to the buf-
fer complete interrupt enable register DMAC_EBCIER register but starts the next
buffer transfer immediately. In this case software must clear the automatic mode bit
in the DMAC_CTRLB to put the DMAC into ROW 1 of
Table 31-3 on page 479
before the last buffer of the DMAC transfer has completed. The transfer is similar to
that shown in
Figure 31-9 on page 488 . The DMAC transfer flow is shown in Figure
31-10 on page 489 .
Figure 31-9. Multi-buffer DMAC Transfer with Source and Destination Address Auto-reloaded
Address of
Source Layer
Address of
Destination Layer
Source Buffers
Destination Buffers
BlockN
Block2
Block1
Block0
SADDR DADDR