Atmel SAM9X25, Руководство пользователя

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1001
11054A–ATARM–27-Jul-11
SAM9X25
1001
11054A–ATARM–27-Jul-11
SAM9X25
44.7.1.2 Transmitter Clock Management
The transmitter clock is generated from the receiver clock or the divider clock or an external
clock scanned on the TK I/O pad. The transmitter clock is selected by the CKS field in
SSC_TCMR (Transmit Clock Mode Register). Transmit Clock can be inverted independently by
the CKI bits in SSC_TCMR.
The transmitter can also drive the TK I/O pad continuously or be limited to the actual data trans-
fer. The clock output is configured by the SSC_TCMR register. The Transmit Clock Inversion
(CKI) bits have no effect on the clock outputs. Programming the TCMR register to select TK pin
(CKS field) and at the same time Continuous Transmit Clock (CKO field) might lead to unpredict-
able results.
Figure 44-6. Transmitter Clock Management
44.7.1.3 Receiver Clock Management
The receiver clock is generated from the transmitter clock or the divider clock or an external
clock scanned on the RK I/O pad. The Receive Clock is selected by the CKS field in
SSC_RCMR (Receive Clock Mode Register). Receive Clocks can be inverted independently by
the CKI bits in SSC_RCMR.
The receiver can also drive the RK I/O pad continuously or be limited to the actual data transfer.
The clock output is configured by the SSC_RCMR register. The Receive Clock Inversion (CKI)
bits have no effect on the clock outputs. Programming the RCMR register to select RK pin (CKS
field) and at the same time Continuous Receive Clock (CKO field) can lead to unpredictable
results.
Table 44-4.
Maximum Minimum
MCK / 2 MCK / 8190
TK (pin)
Receiver
Clock
Divider
Clock
CKS
CKO
Data Transfer
CKI
CKG
Transmitter
Clock
Clock
Output
MUX Tri_state
Controller
Tri-state
Controller
INV
MUX