Atmel SAM9X25, Руководство пользователя

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SAM9X25
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SAM9X25
Figure 21-2. Slow Clock
RCEN, OSC32EN,OSCSEL and OSC32BYP bits are located in the Slow Clock Control Register
(SCKCR) located at address 0xFFFFFE50 in the backed up part of the System Controller and so
are preserved while VDDBU is present.
After a VDDBU power on reset, the default configuration is RCEN = 1, OSC32EN = 0 and OSC-
SEL = 0, BYPASS = 0, allowing the system to start on the internal 32 kHz RC oscillator.
The programmer controls the slow clock switching by software and so must take precautions
during the switching phase.
21.4.1 Switch from Internal 32 kHz RC Oscillator to the 32,768 Hz Crystal
To switch from internal 32 kHz RC oscillator to the 32,768 Hz crystal, the programmer must exe-
cute the following sequence:
• Switch the master clock to a source different from slow clock (PLL or Main Oscillator) through
the Power Management Controller.
• Enable the 32,768 Hz oscillator by setting the bit OSC32EN to 1.
• Wait 32,768 Hz Startup Time for clock stabilization (software loop).
• Switch from internal 32 kHz RC to 32,768 Hz oscillator by setting the bit OSCSEL to 1.
• Wait 5 slow clock cycles for internal resynchronization.
• Disable the 32 kHz RC oscillator by setting the bit RCEN to 0.
• Switch the master clock back to the slow clock domain
21.4.2 Bypass the 32768 Hz Oscillator
The following step must be added to bypass the 32768 Hz Oscillator.
• An external clock must be connected on XIN32.
• Enable the bypass path OSC32BYP bit set to 1.
• Disable the 32768 Hz oscillator by setting the bit OSC32EN to 0.
On Chip
RC OSC
Slow Clock
SLCK
XIN32
XOUT32
Slow Clock
Oscillator
Clock Generator
OSC32EN
RCEN
OSCSEL
OSC32BYP