Atmel SAM9X25, Руководство пользователя

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529
11054A–ATARM–27-Jul-11
SAM9X25
529
11054A–ATARM–27-Jul-11
SAM9X25
Memory access errors (abort, misalignment) lead to an “Unrecoverable Error” indicated by the
corresponding flag in the host controller operational registers.
The USB root hub is integrated in the USB host. Several USB downstream ports are available.
The number of downstream ports can be determined by the software driver reading the root
hub’s operational registers. Device connection is automatically detected by the USB host port
logic.
USB physical transceivers are integrated in the product and driven by the root hub’s ports.
Over current protection on ports can be activated by the USB host controller. Atmel’s standard
product does not dedicate pads to external over current protection.
32.4 Product Dependencies
32.4.1 I/O Lines
HFSDPs, HFSDMs, HHSDPs and HHSDMs are not controlled by any PIO controllers. The
embedded USB High Speed physical transceivers are controlled by the USB host controller.
One transceiver is shared with the USB High Speed Device. In this case USB Host High Speed
Controller uses only Port B, i.e., the signals HFSDPB, HFSDMB, HHSDPB and HHSDMB.
The port A is driven by the USB High Speed Device, the output signals are DFSDP, DFSDM,
DHSDP and DHSDM.
The transceiver is automatically selected for Device operation once the USB High Speed Device
is enabled.
One transceiver is shared with USB Device High Speed. In this case USB Host High Speed
Controller uses only Port A, i.e., the signals HFSDPA, HFSDMA, HHSDPA and HHSDMA.
The port B is driven by the USB Device High Speed, the output signals are DFSDP, DFSDM,
DHSDP and DHSDM.
The transceiver is automatically selected for Device operation once the USB Device High Speed
is enabled.
32.4.2 Power Management
The USB Host High Speed requires a 48 MHz clock for the embedded High-speed transceivers.
This clock is provided by the UTMI PLL, it is UPLLCK.
In case power consumption is saved by stopping the UTMI PLL, high-speed operations are not
possible. Nevertheless, OHCI Full-speed operations remain possible by selecting PLLACK as
the input clock of OHCI.
The High-speed transceiver returns a 30 MHz clock to the USB Host controller.
The USB Host controller requires 48 MHz and 12 MHz clocks for OHCI full-speed operations.
These clocks must be generated by a PLL with a correct accuracy of ± 0.25% thanks to USBDIV
field.
Thus the USB Host peripheral receives three clocks from the Power Management Controller
(PMC): the Peripheral Clock (MCK domain), the UHP48M and the UHP12M (built-in UHP48M
divided by four) used by the OHCI to interface with the bus USB signals (Recovered 12 MHz
domain) in Full-speed operations.
For High-speed operations, the user has to perform the following: