Atmel SAM9X25, Руководство пользователя

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11054A–ATARM–27-Jul-11
SAM9X25
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11054A–ATARM–27-Jul-11
SAM9X25
the case of four simultaneous read accesses, when the four banks and associated rows are
open, the controller reads with a continuous flow and masks the cas latency for each different
access. To allow a continuous flow, the read command must be set at 2 or 3 cycles (cas latency)
before the end of current access. This requires that the scheme of arbitration changes since the
round-robin arbitration cannot be respected. If the controller anticipates a read access, and thus
before the end of current access a master with a high priority arises, then this master will not
serviced.
The arbitration mechanism reduces latency when conflicts occur, i.e., when two or more masters
try to access the SDRAM device at the same time.
The arbitration type is round-robin arbitration. This algorithm dispatches the requests from differ-
ent masters to the SDRAM device in a round-robin manner. If two or more master requests arise
at the same time, the master with the lowest number is serviced first, then the others are ser-
viced in a round-robin manner. To avoid burst breaking and to provide the maximum throughput
for the SDRAM device, arbitration may only take place during the following cycles:
1. Idle cycles: When no master is connected to the SDRAM device.
2. Single cycles: When a slave is currently doing a single access.
3. End of Burst cycles: When the current cycle is the last cycle of a burst transfer. For
bursts of defined length, predicted end of burst matches the size of the transfer. For
bursts of undefined length, predicted end of burst is generated at the end of each four
beat boundary inside the INCR transfer.
4. Anticipated Access: When an anticipate read access is done while current access is
not complete, the arbitration scheme can be changed if the anticipated access is not
the next access serviced by the arbitration scheme.
Figure 30-25. Anticipate Precharge/Active Command in Bank 2 during Read Access in Bank 1
NOP READ NOP
0
NOP PRECH ACT READ
1 1 2
Anticipate command, Precharge/Active Bank 2
Trp
Read access in Bank 1
SDClK
A[12:0]
COMMAND
BA[1:0]
DQS[1:0]
Da
Db
Dc
Dd De Df Dg Dh Di Dj Dk Dl
D[15:0]
3
DM1:0]