AT32F421
Series Reference Manual
2022.11.11
Page 217
Rev 2.02
count clock period (DIV[15:0]+1). Similar to the TMRx_PR register, when the periodic buffer is enabled,
the value in the TMRx_DIV register is updated to the shadow register at an overflow event.
Reading the TMRx_CNT register returns to the current counter value, and writing to the TMRx_CNT
register updates the current counter value to the value being written.
An overflow event is generated by default. Set OVFEN=1 in the TMRx_CTRL1 to disable generation of
update events. The OVFS bit in the TMRx_CTRL1 register is used to select overflow event source. By
default, counter overflow/underflow, setting OVFSWTR bit and the reset signal generated by the slave
timer controller in reset mode trigger the generation of an overflow event. When the OVFS bit is set, only
counter overflow/underflow triggers an overflow event.
Setting the TMREN bit (TMREN=1) enables the timer to start counting. Base on synchronization logic,
however, the actual enable signal TMR_EN is set 1 clock cycle after the TMREN is set.
Figure 14-56 Counter structure
Overflow event
(RPR_overflow)
Overflow event
TMRx_PR
Preload
Overflow event
PR_shadow
1
0
TMRx_DIV
Preload
PRBEN
DIV_shadow
0
1
PRBEN
DIV_counter
CNT_counter
RPR_counter
RPR_shadow
Preload
TMRx_RPR
CNT_overflow
TMR_CLK
DIV_overflow
Upcounting mode
Set CMSEL[1:0]=2’b00 and OWCDIR=1’b0 in the TMRx_CTRL1 register to enable upcounting mode. In
upcounting mode, the counter counts from 0 to the value programmed in the TMRx_PR register, restarts
from 0, and generates an overflow event, with the OVFIF bit being set to 1. If the overflow event is
disabled, the register is no longer reloaded with the preload and re-loaded value after counter overflow
occurs; otherwise, the prescaler and re-loaded value will be updated at an overflow event.
Figure 14-57 Overflow event when PRBEN=0
0
1
2
3
...
31
32
0
1
2
3
...
31
32
0
1
2
3
COUNTER
31
32
0
1
32
...
PR[15:0]
OVFIF
TMR_CLK
0
DIV[15:0]
22
Clear
Clear
Clear
Figure 14-58 Overflow event when PRBEN=1
0
1
2
3
...
31
32
0
1
2
3
...
31
32
0
1
2
3
COUNTER
31
32
0
1
32
...
PR[15:0]
OVFIF
TMR_CLK
0
DIV[15:0]
22
Clear
Clear
Clear
Repetition counter mode:
The TMRx_RPR register is used to configure the counting period of repetition counter. The repletion
counter mode is enabled when the repetition counter value is not equal to 0. In this mode, an overflow
event occurs once at every counter overflow (RPR[7:0]+1), and the repetition counter is decremented at